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MC74HC589ADR2G
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onsemi Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MC74HC589ADR2G
onsemi · Shift Registers · SOIC-16
MC74HC589ADR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Parallel data input B; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 2 | C | input | Parallel data input C; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 3 | D | input | Parallel data input D; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 4 | E | input | Parallel data input E; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 5 | F | input | Parallel data input F; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 6 | G | input | Parallel data input G; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 7 | H | input | Parallel data input H; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 8 | GND | power_in | Ground pin (pin 8 per the logic diagram); all voltages are referenced to this pin. |
| 9 | QH | tri_state | Serial data output from the last stage of the shift register; this is a 3-state output that goes high-impedance when Output Enable is high. |
| 10 | Output Enable | input | Active-low output enable; a high level forces QH into the high-impedance state, a low level enables the output, and it does not affect the input latch or shift register. |
| 11 | Shift Clock | input | Serial shift clock; a low-to-high transition shifts the serial input into the shift register and shifts stage H out to QH. |
| 12 | Latch Clock | input | Data latch clock; a low-to-high transition loads the parallel data on inputs A-H into the data latch. |
| 13 | Serial Shift/Parallel Load | input | Shift register mode control; a high level allows serial shifting, while a low level makes the shift register accept parallel data from the data latch. |
| 14 | SA | input | Serial data input; data is shifted into the shift register on the rising edge of Shift Clock only when Serial Shift/Parallel Load is high and is ignored when it is low. |
| 15 | A | input | Parallel data input A; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 16 | VCC | power_in | Positive supply pin (pin 16 per the logic diagram); recommended DC supply range is 2.0 V to 6.0 V referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage (referenced to GND) | VCC | 2 | 6 | V | 3 | ||
| DC input voltage, output voltage (referenced to GND) | Vin, Vout | 0 | V | max = VCC | 3 | ||
| Operating temperature, all package types | TA | -55 | 125 | °C | 3 | ||
| Input rise and fall time | tr, tf | 1000 | ns | VCC = 2.0 V (Figure 3) | 3 | ||
| Input rise and fall time | tr, tf | 800 | ns | VCC = 3.0 V (Figure 3) | 3 | ||
| Input rise and fall time | tr, tf | 500 | ns | VCC = 4.5 V (Figure 3) | 3 | ||
| Input rise and fall time | tr, tf | 400 | ns | VCC = 6.0 V (Figure 3) | 3 | ||
| DC supply voltage (referenced to GND) | VCC | -0.5 | 7 | V | 3 | ||
| DC input voltage (referenced to GND) | Vin | -0.5 | V | upper limit printed as VCC + 0.5 V | 3 | ||
| DC output voltage (referenced to GND) | Vout | -0.5 | V | upper limit printed as VCC + 0.5 V | 3 | ||
| DC input current, per pin | Iin | 20 | mA | per pin | 3 | ||
| DC output current, per pin | Iout | 35 | mA | per pin | 3 | ||
| DC supply current, VCC and GND pins | ICC | 75 | mA | VCC and GND pins | 3 | ||
| DC ground current per ground pin | IGND | 75 | mA | per ground pin | 3 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 3 | ||
| Lead temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 3 | ||
| Junction temperature under bias | TJ | 150 | °C | under bias | 3 | ||
| Thermal resistance, junction-to-ambient | θJA | 112 | °C/W | SOIC package | 3 | ||
| Power dissipation in still air | PD | 500 | mW | SOIC package, still air at 85 °C | 3 | ||
| ESD withstand voltage, Human Body Model | VESD | 4000 | V | Human Body Model, EIA/JESD22-A114-A | 3 | ||
| Minimum high-level input voltage | VIH | 1.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Minimum high-level input voltage | VIH | 2.1 | V | VCC = 3.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Minimum high-level input voltage | VIH | 3.15 | V | VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Minimum high-level input voltage | VIH | 4.2 | V | VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Maximum low-level input voltage | VIL | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Maximum low-level input voltage | VIL | 0.9 | V | VCC = 3.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Maximum low-level input voltage | VIL | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Maximum low-level input voltage | VIL | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Minimum high-level output voltage | VOH | 1.9 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 | ||
| Minimum high-level output voltage | VOH | 4.4 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 | ||
| Minimum high-level output voltage | VOH | 5.9 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 | ||
| Minimum high-level output voltage | VOH | 2.2 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; 125 °C | 4 | ||
| Minimum high-level output voltage | VOH | 3.7 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; 125 °C | 4 | ||
| Minimum high-level output voltage | VOH | 5.2 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 7.8 mA; 125 °C | 4 | ||
| Maximum low-level output voltage | VOL | 0.1 | V | VCC = 2.0 V; Vin = VIH; /Iout/ ≤ 20 µA | 4 | ||
| Maximum low-level output voltage | VOL | 0.4 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; 125 °C | 4 | ||
| Maximum input leakage current | Iin | 1 | µA | VCC = 6.0 V; Vin = VCC or GND; 125 °C | 4 | ||
| Maximum three-state leakage current, output in high-impedance state | IOZ | 10 | µA | VCC = 6.0 V; Vin = VIL or VIH; Vout = VCC or GND; 125 °C | 4 | ||
| Maximum quiescent supply current (per package) | ICC | 160 | µA | VCC = 6.0 V; Vin = VCC or GND; Iout = 0 A; 125 °C | 4 | ||
| Maximum propagation delay, Latch Clock to QH | tPLH, tPHL | 275 | ns | VCC = 2.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 3 and 10; 125 °C | 5 | ||
| Maximum propagation delay, Latch Clock to QH | tPLH, tPHL | 125 | ns | VCC = 3.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 3 and 10; 125 °C | 5 | ||
| Maximum propagation delay, Latch Clock to QH | tPLH, tPHL | 60 | ns | VCC = 4.5 V; CL = 50 pF; tr = tf = 6 ns; Figures 3 and 10; 125 °C | 5 | ||
| Maximum propagation delay, Latch Clock to QH | tPLH, tPHL | 50 | ns | VCC = 6.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 3 and 10; 125 °C | 5 | ||
| Maximum propagation delay, Shift Clock to QH | tPLH, tPHL | 240 | ns | VCC = 2.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 4 and 10; 125 °C | 5 | ||
| Maximum propagation delay, Shift Clock to QH | tPLH, tPHL | 160 | ns | VCC = 3.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 4 and 10; 125 °C | 5 | ||
| Maximum propagation delay, Shift Clock to QH | tPLH, tPHL | 48 | ns | VCC = 4.5 V; CL = 50 pF; tr = tf = 6 ns; Figures 4 and 10; 125 °C | 5 | ||
| Maximum propagation delay, Shift Clock to QH | tPLH, tPHL | 40 | ns | VCC = 6.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 4 and 10; 125 °C | 5 | ||
| Minimum setup time, A−H to Latch Clock | tsu | 150 | ns | VCC = 2.0 V; Figure 7; 125 °C | 6 | ||
| Minimum setup time, A−H to Latch Clock | tsu | 60 | ns | VCC = 3.0 V; Figure 7; 125 °C | 6 | ||
| Minimum setup time, A−H to Latch Clock | tsu | 30 | ns | VCC = 4.5 V; Figure 7; 125 °C | 6 | ||
| Minimum setup time, A−H to Latch Clock | tsu | 26 | ns | VCC = 6.0 V; Figure 7; 125 °C | 6 | ||
| Minimum setup time, Serial Data Input SA to Shift Clock | tsu | 150 | ns | VCC = 2.0 V; Figure 8; 125 °C | 6 | ||
| Minimum setup time, Serial Data Input SA to Shift Clock | tsu | 60 | ns | VCC = 3.0 V; Figure 8; 125 °C | 6 | ||
| Minimum setup time, Serial Data Input SA to Shift Clock | tsu | 30 | ns | VCC = 4.5 V; Figure 8; 125 °C | 6 | ||
| Minimum setup time, Serial Data Input SA to Shift Clock | tsu | 26 | ns | VCC = 6.0 V; Figure 8; 125 °C | 6 | ||
| Maximum input capacitance | Cin | 10 | pF | 5 |
CAD (KiCad official)
- Symbol:
MC74HC589ADR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hc589adr2g-etched.step/mc74hc589adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc589adr2g.step/mc74hc589adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (14 pp, sha256
75eadeb0d78f93a9, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HC589ADR2G
**onsemi** · Shift Registers · SOIC-16
MC74HC589ADR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Parallel data input B; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 2 | C | input | Parallel data input C; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 3 | D | input | Parallel data input D; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 4 | E | input | Parallel data input E; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 5 | F | input | Parallel data input F; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 6 | G | input | Parallel data input G; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 7 | H | input | Parallel data input H; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 8 | GND | power_in | Ground pin (pin 8 per the logic diagram); all voltages are referenced to this pin. |
| 9 | QH | tri_state | Serial data output from the last stage of the shift register; this is a 3-state output that goes high-impedance when Output Enable is high. |
| 10 | Output Enable | input | Active-low output enable; a high level forces QH into the high-impedance state, a low level enables the output, and it does not affect the input latch or shift register. |
| 11 | Shift Clock | input | Serial shift clock; a low-to-high transition shifts the serial input into the shift register and shifts stage H out to QH. |
| 12 | Latch Clock | input | Data latch clock; a low-to-high transition loads the parallel data on inputs A-H into the data latch. |
| 13 | Serial Shift/Parallel Load | input | Shift register mode control; a high level allows serial shifting, while a low level makes the shift register accept parallel data from the data latch. |
| 14 | SA | input | Serial data input; data is shifted into the shift register on the rising edge of Shift Clock only when Serial Shift/Parallel Load is high and is ignored when it is low. |
| 15 | A | input | Parallel data input A; data on this pin is stored in the data latch on the rising edge of the Latch Clock input. |
| 16 | VCC | power_in | Positive supply pin (pin 16 per the logic diagram); recommended DC supply range is 2.0 V to 6.0 V referenced to GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage (referenced to GND) | VCC | 2 | | 6 | V | | 3 |
| DC input voltage, output voltage (referenced to GND) | Vin, Vout | 0 | | | V | max = VCC | 3 |
| Operating temperature, all package types | TA | -55 | | 125 | °C | | 3 |
| Input rise and fall time | tr, tf | | | 1000 | ns | VCC = 2.0 V (Figure 3) | 3 |
| Input rise and fall time | tr, tf | | | 800 | ns | VCC = 3.0 V (Figure 3) | 3 |
| Input rise and fall time | tr, tf | | | 500 | ns | VCC = 4.5 V (Figure 3) | 3 |
| Input rise and fall time | tr, tf | | | 400 | ns | VCC = 6.0 V (Figure 3) | 3 |
| DC supply voltage (referenced to GND) | VCC | -0.5 | | 7 | V | | 3 |
| DC input voltage (referenced to GND) | Vin | -0.5 | | | V | upper limit printed as VCC + 0.5 V | 3 |
| DC output voltage (referenced to GND) | Vout | -0.5 | | | V | upper limit printed as VCC + 0.5 V | 3 |
| DC input current, per pin | Iin | | | 20 | mA | per pin | 3 |
| DC output current, per pin | Iout | | | 35 | mA | per pin | 3 |
| DC supply current, VCC and GND pins | ICC | | | 75 | mA | VCC and GND pins | 3 |
| DC ground current per ground pin | IGND | | | 75 | mA | per ground pin | 3 |
| Storage temperature range | TSTG | -65 | | 150 | °C | | 3 |
| Lead temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds | 3 |
| Junction temperature under bias | TJ | | | 150 | °C | under bias | 3 |
| Thermal resistance, junction-to-ambient | θJA | | 112 | | °C/W | SOIC package | 3 |
| Power dissipation in still air | PD | | | 500 | mW | SOIC package, still air at 85 °C | 3 |
| ESD withstand voltage, Human Body Model | VESD | | | 4000 | V | Human Body Model, EIA/JESD22-A114-A | 3 |
| Minimum high-level input voltage | VIH | 1.5 | | | V | VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |
| Minimum high-level input voltage | VIH | 2.1 | | | V | VCC = 3.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |
| Minimum high-level input voltage | VIH | 3.15 | | | V | VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |
| Minimum high-level input voltage | VIH | 4.2 | | | V | VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |
| Maximum low-level input voltage | VIL | | | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |
| Maximum low-level input voltage | VIL | | | 0.9 | V | VCC = 3.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |
| Maximum low-level input voltage | VIL | | | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |
| Maximum low-level input voltage | VIL | | | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |
| Minimum high-level output voltage | VOH | 1.9 | | | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 |
| Minimum high-level output voltage | VOH | 4.4 | | | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 |
| Minimum high-level output voltage | VOH | 5.9 | | | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 |
| Minimum high-level output voltage | VOH | 2.2 | | | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; 125 °C | 4 |
| Minimum high-level output voltage | VOH | 3.7 | | | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; 125 °C | 4 |
| Minimum high-level output voltage | VOH | 5.2 | | | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 7.8 mA; 125 °C | 4 |
| Maximum low-level output voltage | VOL | | | 0.1 | V | VCC = 2.0 V; Vin = VIH; /Iout/ ≤ 20 µA | 4 |
| Maximum low-level output voltage | VOL | | | 0.4 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; 125 °C | 4 |
| Maximum input leakage current | Iin | | | 1 | µA | VCC = 6.0 V; Vin = VCC or GND; 125 °C | 4 |
| Maximum three-state leakage current, output in high-impedance state | IOZ | | | 10 | µA | VCC = 6.0 V; Vin = VIL or VIH; Vout = VCC or GND; 125 °C | 4 |
| Maximum quiescent supply current (per package) | ICC | | | 160 | µA | VCC = 6.0 V; Vin = VCC or GND; Iout = 0 A; 125 °C | 4 |
| Maximum propagation delay, Latch Clock to QH | tPLH, tPHL | | | 275 | ns | VCC = 2.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 3 and 10; 125 °C | 5 |
| Maximum propagation delay, Latch Clock to QH | tPLH, tPHL | | | 125 | ns | VCC = 3.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 3 and 10; 125 °C | 5 |
| Maximum propagation delay, Latch Clock to QH | tPLH, tPHL | | | 60 | ns | VCC = 4.5 V; CL = 50 pF; tr = tf = 6 ns; Figures 3 and 10; 125 °C | 5 |
| Maximum propagation delay, Latch Clock to QH | tPLH, tPHL | | | 50 | ns | VCC = 6.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 3 and 10; 125 °C | 5 |
| Maximum propagation delay, Shift Clock to QH | tPLH, tPHL | | | 240 | ns | VCC = 2.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 4 and 10; 125 °C | 5 |
| Maximum propagation delay, Shift Clock to QH | tPLH, tPHL | | | 160 | ns | VCC = 3.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 4 and 10; 125 °C | 5 |
| Maximum propagation delay, Shift Clock to QH | tPLH, tPHL | | | 48 | ns | VCC = 4.5 V; CL = 50 pF; tr = tf = 6 ns; Figures 4 and 10; 125 °C | 5 |
| Maximum propagation delay, Shift Clock to QH | tPLH, tPHL | | | 40 | ns | VCC = 6.0 V; CL = 50 pF; tr = tf = 6 ns; Figures 4 and 10; 125 °C | 5 |
| Minimum setup time, A−H to Latch Clock | tsu | 150 | | | ns | VCC = 2.0 V; Figure 7; 125 °C | 6 |
| Minimum setup time, A−H to Latch Clock | tsu | 60 | | | ns | VCC = 3.0 V; Figure 7; 125 °C | 6 |
| Minimum setup time, A−H to Latch Clock | tsu | 30 | | | ns | VCC = 4.5 V; Figure 7; 125 °C | 6 |
| Minimum setup time, A−H to Latch Clock | tsu | 26 | | | ns | VCC = 6.0 V; Figure 7; 125 °C | 6 |
| Minimum setup time, Serial Data Input SA to Shift Clock | tsu | 150 | | | ns | VCC = 2.0 V; Figure 8; 125 °C | 6 |
| Minimum setup time, Serial Data Input SA to Shift Clock | tsu | 60 | | | ns | VCC = 3.0 V; Figure 8; 125 °C | 6 |
| Minimum setup time, Serial Data Input SA to Shift Clock | tsu | 30 | | | ns | VCC = 4.5 V; Figure 8; 125 °C | 6 |
| Minimum setup time, Serial Data Input SA to Shift Clock | tsu | 26 | | | ns | VCC = 6.0 V; Figure 8; 125 °C | 6 |
| Maximum input capacitance | Cin | | | 10 | pF | | 5 |
## CAD (KiCad official)
- Symbol: `MC74HC589ADR2G`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `mc74hc589adr2g-etched.step` / `mc74hc589adr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hc589adr2g.step` / `mc74hc589adr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hc589a-d.pdf) (14 pp, sha256 `75eadeb0d78f93a9`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hc589adr2g-datasheet.pdf)