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MC74HC573ADTR2G

Public Made by Adom

by adom

onsemi Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74HC573ADTR2G

onsemi · Latches · TSSOP-20

MC74HC573ADTR2G from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUTPUT ENABLE input Active-low Output Enable: when this input is high, all eight Q outputs are forced to high impedance (Z) regardless of the latch state.
2 D0 input Data input D0 is latched when Latch Enable goes low, and must meet the specified setup and hold times to Latch Enable; unused inputs must be tied to GND or VCC.
3 D1 input Data input D1 is latched when Latch Enable goes low, and must meet the specified setup and hold times to Latch Enable; unused inputs must be tied to GND or VCC.
4 D2 input Data input D2 is latched when Latch Enable goes low, and must meet the specified setup and hold times to Latch Enable; unused inputs must be tied to GND or VCC.
5 D3 input Data input D3 is latched when Latch Enable goes low, and must meet the specified setup and hold times to Latch Enable; unused inputs must be tied to GND or VCC.
6 D4 input Data input D4 is latched when Latch Enable goes low, and must meet the specified setup and hold times to Latch Enable; unused inputs must be tied to GND or VCC.
7 D5 input Data input D5 is latched when Latch Enable goes low, and must meet the specified setup and hold times to Latch Enable; unused inputs must be tied to GND or VCC.
8 D6 input Data input D6 is latched when Latch Enable goes low, and must meet the specified setup and hold times to Latch Enable; unused inputs must be tied to GND or VCC.
9 D7 input Data input D7 is latched when Latch Enable goes low, and must meet the specified setup and hold times to Latch Enable; unused inputs must be tied to GND or VCC.
10 GND power_in Ground reference for all voltages; Vin and Vout are constrained to the range GND to VCC.
11 LE input Latch Enable: the latches are transparent to data while high and latch the data present at D when it goes low, with minimum pulse width tw applying.
12 Q7 tri_state Noninverting 3-state output 7, which can drive 15 LSTTL loads and is high impedance when Output Enable is high.
13 Q6 tri_state Noninverting 3-state output 6, which can drive 15 LSTTL loads and is high impedance when Output Enable is high.
14 Q5 tri_state Noninverting 3-state output 5, which can drive 15 LSTTL loads and is high impedance when Output Enable is high.
15 Q4 tri_state Noninverting 3-state output 4, which can drive 15 LSTTL loads and is high impedance when Output Enable is high.
16 Q3 tri_state Noninverting 3-state output 3, which can drive 15 LSTTL loads and is high impedance when Output Enable is high.
17 Q2 tri_state Noninverting 3-state output 2, which can drive 15 LSTTL loads and is high impedance when Output Enable is high.
18 Q1 tri_state Noninverting 3-state output 1, which can drive 15 LSTTL loads and is high impedance when Output Enable is high.
19 Q0 tri_state Noninverting 3-state output 0, which can drive 15 LSTTL loads and is high impedance when Output Enable is high.
20 VCC power_in Positive supply, 2.0 V to 6.0 V referenced to GND (recommended operating range).

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage (Referenced to GND) VCC 2 6 V Referenced to GND 2
DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout 0 V Referenced to GND; max = VCC 2
Operating Temperature, All Package Types TA -55 125 C 2
Input Rise and Fall Time tr, tf 0 1000 ns VCC = 2.0 V (Figure 1) 2
Input Rise and Fall Time tr, tf 0 500 ns VCC = 4.5 V (Figure 1) 2
Input Rise and Fall Time tr, tf 0 400 ns VCC = 6.0 V (Figure 1) 2
DC Supply Voltage (Referenced to GND) VCC -0.5 7 V 2
DC Input Current, per Pin Iin -20 20 mA per pin 2
DC Output Current, per Pin Iout -35 35 mA per pin 2
DC Supply Current, VCC and GND Pins ICC -75 75 mA VCC and GND pins 2
Power Dissipation in Still Air, TSSOP Package PD 450 mW Still air, TSSOP package 2
Storage Temperature Tstg -65 150 C 2
Minimum High-Level Input Voltage VIH 1.5 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V 2
Minimum High-Level Input Voltage VIH 2.1 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 3.0 V 2
Minimum High-Level Input Voltage VIH 3.15 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 4.5 V 2
Minimum High-Level Input Voltage VIH 4.2 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 6.0 V 2
Maximum Low-Level Input Voltage VIL 0.5 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V 2
Maximum Low-Level Input Voltage VIL 0.9 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 3.0 V 2
Maximum Low-Level Input Voltage VIL 1.35 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 4.5 V 2
Maximum Low-Level Input Voltage VIL 1.8 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 6.0 V 2
Minimum High-Level Output Voltage VOH 1.9 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 2.0 V 2
Minimum High-Level Output Voltage VOH 4.4 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 4.5 V 2
Minimum High-Level Output Voltage VOH 5.9 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 6.0 V 2
Minimum High-Level Output Voltage VOH 2.2 V Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V 2
Minimum High-Level Output Voltage VOH 3.7 V Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; VCC = 4.5 V 2
Minimum High-Level Output Voltage VOH 5.2 V Vin = VIH or VIL; /Iout/ ≤ 7.8 mA; VCC = 6.0 V 2
Maximum Low-Level Output Voltage VOL 0.1 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V 2
Maximum Low-Level Output Voltage VOL 0.4 V Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V 2
Maximum Input Leakage Current Iin -1 1 µA Vin = VCC or GND; VCC = 6.0 V 2
Maximum Three-State Leakage Current IOZ -10 10 µA Output in high-impedance state; Vin = VIL or VIH; Vout = VCC or GND; VCC = 6.0 V 2
Maximum Quiescent Supply Current (per Package) ICC 160 µA Vin = VCC or GND; /Iout/ = 0 µA; VCC = 6.0 V 2
Maximum Propagation Delay, Input D to Q tPLH, tPHL 225 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 2.0 V (Figures 1 and 5) 3
Maximum Propagation Delay, Input D to Q tPLH, tPHL 180 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 3.0 V (Figures 1 and 5) 3
Maximum Propagation Delay, Input D to Q tPLH, tPHL 45 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 4.5 V (Figures 1 and 5) 3
Maximum Propagation Delay, Input D to Q tPLH, tPHL 38 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 6.0 V (Figures 1 and 5) 3
Maximum Propagation Delay, Latch Enable to Q tPLH, tPHL 240 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 2.0 V (Figures 2 and 5) 3
Maximum Propagation Delay, Latch Enable to Q tPLH, tPHL 190 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 3.0 V (Figures 2 and 5) 3
Maximum Propagation Delay, Latch Enable to Q tPLH, tPHL 48 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 4.5 V (Figures 2 and 5) 3
Maximum Propagation Delay, Latch Enable to Q tPLH, tPHL 41 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 6.0 V (Figures 2 and 5) 3
Maximum Propagation Delay, Output Enable to Q tPLZ, tPHZ 225 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 2.0 V (Figures 3 and 6) 3
Maximum Propagation Delay, Output Enable to Q tPLZ, tPHZ 150 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 3.0 V (Figures 3 and 6) 3
Maximum Propagation Delay, Output Enable to Q tPLZ, tPHZ 45 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 4.5 V (Figures 3 and 6) 3
Maximum Propagation Delay, Output Enable to Q tPLZ, tPHZ 38 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 6.0 V (Figures 3 and 6) 3
Maximum Output Transition Time, Any Output tTLH, tTHL 90 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 2.0 V (Figures 1 and 5) 3
Maximum Output Transition Time, Any Output tTLH, tTHL 36 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 3.0 V (Figures 1 and 5) 3
Maximum Output Transition Time, Any Output tTLH, tTHL 18 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 4.5 V (Figures 1 and 5) 3
Maximum Output Transition Time, Any Output tTLH, tTHL 15 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 6.0 V (Figures 1 and 5) 3
Maximum Input Capacitance Cin 10 pF 3
Minimum Setup Time, Input D to Latch Enable tsu 75 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 2.0 V (Figure 4) 3
Minimum Setup Time, Input D to Latch Enable tsu 60 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 3.0 V (Figure 4) 3
Minimum Setup Time, Input D to Latch Enable tsu 15 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 4.5 V (Figure 4) 3
Minimum Setup Time, Input D to Latch Enable tsu 13 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 6.0 V (Figure 4) 3
Minimum Pulse Width, Latch Enable tw 110 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 2.0 V (Figure 2) 3
Minimum Pulse Width, Latch Enable tw 90 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 3.0 V (Figure 2) 3
Minimum Pulse Width, Latch Enable tw 22 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 4.5 V (Figure 2) 3
Minimum Pulse Width, Latch Enable tw 19 ns CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 6.0 V (Figure 2) 3

CAD (KiCad official)

  • Symbol: MC74HC573ADTR2G
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: mc74hc573adtr2g-etched.step / mc74hc573adtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hc573adtr2g.step / mc74hc573adtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (7 pp, sha256 2d71272529fede93, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF