component
MC74HC541ADTG
Public Made by Adomby adom
onsemi Buffers / Drivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MC74HC541ADTG
onsemi · Buffers / Drivers · TSSOP-20
MC74HC541ADTG from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Active-low output enable; with OE2 low the outputs are enabled, and a high level on either OE input puts the outputs in high impedance. |
| 2 | A1 | input | Data input 1; appears non-inverted on Y1 when outputs are enabled. |
| 3 | A2 | input | Data input 2; appears non-inverted on Y2 when outputs are enabled. |
| 4 | A3 | input | Data input 3; appears non-inverted on Y3 when outputs are enabled. |
| 5 | A4 | input | Data input 4; appears non-inverted on Y4 when outputs are enabled. |
| 6 | A5 | input | Data input 5; appears non-inverted on Y5 when outputs are enabled. |
| 7 | A6 | input | Data input 6; appears non-inverted on Y6 when outputs are enabled. |
| 8 | A7 | input | Data input 7; appears non-inverted on Y7 when outputs are enabled. |
| 9 | A8 | input | Data input 8; appears non-inverted on Y8 when outputs are enabled. |
| 10 | GND | power_in | Ground pin (0 V reference). |
| 11 | Y8 | tri_state | Non-inverting 3-state output 8, high impedance when either output enable is high. |
| 12 | Y7 | tri_state | Non-inverting 3-state output 7, high impedance when either output enable is high. |
| 13 | Y6 | tri_state | Non-inverting 3-state output 6, high impedance when either output enable is high. |
| 14 | Y5 | tri_state | Non-inverting 3-state output 5, high impedance when either output enable is high. |
| 15 | Y4 | tri_state | Non-inverting 3-state output 4, high impedance when either output enable is high. |
| 16 | Y3 | tri_state | Non-inverting 3-state output 3, high impedance when either output enable is high. |
| 17 | Y2 | tri_state | Non-inverting 3-state output 2, high impedance when either output enable is high. |
| 18 | Y1 | tri_state | Non-inverting 3-state output 1, high impedance when either output enable is high. |
| 19 | OE2 | input | Active-low output enable; with OE1 low the outputs are enabled, and a high level on either OE input puts the outputs in high impedance. |
| 20 | VCC | power_in | Supply voltage pin, operating range 2.0 to 6.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-20 |
| Category | Logic ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 7 | V | 2 | ||
| DC Input Voltage | VI | -0.5 | V | -0.5 ≤ VI ≤ VCC + 0.5 | 2 | ||
| DC Output Voltage | VO | -0.5 | V | -0.5 ≤ VO ≤ VCC + 0.5; IO absolute maximum rating must be observed | 2 | ||
| DC Input Diode Current | IIK | -20 | 20 | mA | 2 | ||
| DC Output Diode Current | IOK | -35 | 35 | mA | 2 | ||
| DC Output Sink Current | IO | -35 | 35 | mA | 2 | ||
| DC Supply Current per Supply Pin | ICC | -75 | 75 | mA | 2 | ||
| DC Ground Current per Ground Pin | IGND | -75 | 75 | mA | 2 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 2 | ||
| Junction Temperature under Bias | TJ | 150 | °C | 2 | |||
| ESD Withstand Voltage, Human Body Model | VESD | 4000 | V | > 4000; tested to EIA/JESD22-A114-A | 2 | ||
| ESD Withstand Voltage, Machine Model | VESD | 300 | V | > 300; tested to EIA/JESD22-A115-A | 2 | ||
| ESD Withstand Voltage, Charged Device Model | VESD | 1000 | V | > 1000; tested to JESD22-C101-A | 2 | ||
| Latchup Performance | ILatchup | -300 | 300 | mA | Above VCC and below GND at 85°C; tested to EIA/JESD78 | 2 | |
| Thermal Resistance, TSSOP | θJA | 128 | °C/W | TSSOP | 2 | ||
| Power Dissipation in Still Air, TSSOP | PD | 450 | mW | At 85°C, TSSOP | 2 | ||
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | 2 | ||
| DC Input Voltage, Output Voltage (Referenced to GND) | VIN, VOUT | 0 | V | 0 to VCC | 2 | ||
| Operating Temperature Range, All Package Types | TA | -55 | 125 | °C | 2 | ||
| Input Rise/Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V | 2 | |
| Input Rise/Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V | 2 | |
| Input Rise/Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V | 2 | |
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V; VOUT = 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC = 4.5 V; VOUT = 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | VCC = 6.0 V; VOUT = 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC = 2.0 V; VOUT = VCC - 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | VCC = 4.5 V; VOUT = VCC - 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | VCC = 6.0 V; VOUT = VCC - 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC = 4.5 V; VIN = VIL, /IOUT/ ≤ 20 µA; all temperature columns | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.98 | V | VCC = 4.5 V; VIN = VIL, /IOUT/ ≤ 6.0 mA; -55 to 25°C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.84 | V | VCC = 4.5 V; VIN = VIL, /IOUT/ ≤ 6.0 mA; ≤85°C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | VCC = 4.5 V; VIN = VIL, /IOUT/ ≤ 6.0 mA; ≤125°C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC = 4.5 V; VIN = VIH, /IOUT/ ≤ 20 µA; all temperature columns | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.26 | V | VCC = 4.5 V; VIN = VIH, /IOUT/ ≤ 6.0 mA; -55 to 25°C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.33 | V | VCC = 4.5 V; VIN = VIH, /IOUT/ ≤ 6.0 mA; ≤85°C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | VCC = 4.5 V; VIN = VIH, /IOUT/ ≤ 6.0 mA; ≤125°C | 3 | ||
| Maximum Input Leakage Current | IIN | -0.1 | 0.1 | µA | VIN = VCC or GND; VCC = 6.0 V; -55 to 25°C | 3 | |
| Maximum Input Leakage Current | IIN | -1 | 1 | µA | VIN = VCC or GND; VCC = 6.0 V; ≤85°C | 3 | |
| Maximum 3-State Leakage Current | IOZ | -0.5 | 0.5 | µA | Output in high impedance state; VIN = VIL or VIH; VOUT = VCC or GND; VCC = 6.0 V; -55 to 25°C | 3 | |
| Maximum 3-State Leakage Current | IOZ | -5 | 5 | µA | Output in high impedance state; VIN = VIL or VIH; VOUT = VCC or GND; VCC = 6.0 V; ≤85°C | 3 | |
| Maximum 3-State Leakage Current | IOZ | -10 | 10 | µA | Output in high impedance state; VIN = VIL or VIH; VOUT = VCC or GND; VCC = 6.0 V; ≤125°C | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 4 | µA | VIN = VCC or GND; IOUT = 0 µA; VCC = 6.0 V; -55 to 25°C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 40 | µA | VIN = VCC or GND; IOUT = 0 µA; VCC = 6.0 V; ≤85°C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | µA | VIN = VCC or GND; IOUT = 0 µA; VCC = 6.0 V; ≤125°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 18 | ns | VCC = 4.5 V; CL = 50 pF; -55 to 25°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 23 | ns | VCC = 4.5 V; CL = 50 pF; ≤85°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 28 | ns | VCC = 4.5 V; CL = 50 pF; ≤125°C | 3 | ||
| Maximum Propagation Delay, Output Enable to Output Y | tPLZ, tPHZ | 25 | ns | VCC = 4.5 V; CL = 50 pF; -55 to 25°C | 3 | ||
| Maximum Propagation Delay, Output Enable to Output Y | tPLZ, tPHZ | 31 | ns | VCC = 4.5 V; CL = 50 pF; ≤85°C | 3 | ||
| Maximum Propagation Delay, Output Enable to Output Y | tPLZ, tPHZ | 38 | ns | VCC = 4.5 V; CL = 50 pF; ≤125°C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 12 | ns | VCC = 4.5 V; CL = 50 pF; -55 to 25°C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 15 | ns | VCC = 4.5 V; CL = 50 pF; ≤85°C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 18 | ns | VCC = 4.5 V; CL = 50 pF; ≤125°C | 3 | ||
| Maximum Input Capacitance | CIN | 10 | pF | All temperature columns | 3 | ||
| Maximum 3-State Output Capacitance (High Impedance State Output) | COUT | 15 | pF | All temperature columns | 3 | ||
| Power Dissipation Capacitance (Per Buffer) | CPD | 35 | pF | Typical @ 25°C, VCC = 5.0 V, VEE = 0 V | 3 |
CAD (KiCad official)
- Symbol:
MC74HC541ADTG - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
mc74hc541adtg-etched.step/mc74hc541adtg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc541adtg.step/mc74hc541adtg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (8 pp, sha256
da20b133da2c877c, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HC541ADTG
**onsemi** · Buffers / Drivers · TSSOP-20
MC74HC541ADTG from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Active-low output enable; with OE2 low the outputs are enabled, and a high level on either OE input puts the outputs in high impedance. |
| 2 | A1 | input | Data input 1; appears non-inverted on Y1 when outputs are enabled. |
| 3 | A2 | input | Data input 2; appears non-inverted on Y2 when outputs are enabled. |
| 4 | A3 | input | Data input 3; appears non-inverted on Y3 when outputs are enabled. |
| 5 | A4 | input | Data input 4; appears non-inverted on Y4 when outputs are enabled. |
| 6 | A5 | input | Data input 5; appears non-inverted on Y5 when outputs are enabled. |
| 7 | A6 | input | Data input 6; appears non-inverted on Y6 when outputs are enabled. |
| 8 | A7 | input | Data input 7; appears non-inverted on Y7 when outputs are enabled. |
| 9 | A8 | input | Data input 8; appears non-inverted on Y8 when outputs are enabled. |
| 10 | GND | power_in | Ground pin (0 V reference). |
| 11 | Y8 | tri_state | Non-inverting 3-state output 8, high impedance when either output enable is high. |
| 12 | Y7 | tri_state | Non-inverting 3-state output 7, high impedance when either output enable is high. |
| 13 | Y6 | tri_state | Non-inverting 3-state output 6, high impedance when either output enable is high. |
| 14 | Y5 | tri_state | Non-inverting 3-state output 5, high impedance when either output enable is high. |
| 15 | Y4 | tri_state | Non-inverting 3-state output 4, high impedance when either output enable is high. |
| 16 | Y3 | tri_state | Non-inverting 3-state output 3, high impedance when either output enable is high. |
| 17 | Y2 | tri_state | Non-inverting 3-state output 2, high impedance when either output enable is high. |
| 18 | Y1 | tri_state | Non-inverting 3-state output 1, high impedance when either output enable is high. |
| 19 | OE2 | input | Active-low output enable; with OE1 low the outputs are enabled, and a high level on either OE input puts the outputs in high impedance. |
| 20 | VCC | power_in | Supply voltage pin, operating range 2.0 to 6.0 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-20 |
| Category | Logic ICs |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | | 7 | V | | 2 |
| DC Input Voltage | VI | -0.5 | | | V | -0.5 ≤ VI ≤ VCC + 0.5 | 2 |
| DC Output Voltage | VO | -0.5 | | | V | -0.5 ≤ VO ≤ VCC + 0.5; IO absolute maximum rating must be observed | 2 |
| DC Input Diode Current | IIK | -20 | | 20 | mA | | 2 |
| DC Output Diode Current | IOK | -35 | | 35 | mA | | 2 |
| DC Output Sink Current | IO | -35 | | 35 | mA | | 2 |
| DC Supply Current per Supply Pin | ICC | -75 | | 75 | mA | | 2 |
| DC Ground Current per Ground Pin | IGND | -75 | | 75 | mA | | 2 |
| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 2 |
| Lead Temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds | 2 |
| Junction Temperature under Bias | TJ | | | 150 | °C | | 2 |
| ESD Withstand Voltage, Human Body Model | VESD | 4000 | | | V | > 4000; tested to EIA/JESD22-A114-A | 2 |
| ESD Withstand Voltage, Machine Model | VESD | 300 | | | V | > 300; tested to EIA/JESD22-A115-A | 2 |
| ESD Withstand Voltage, Charged Device Model | VESD | 1000 | | | V | > 1000; tested to JESD22-C101-A | 2 |
| Latchup Performance | ILatchup | -300 | | 300 | mA | Above VCC and below GND at 85°C; tested to EIA/JESD78 | 2 |
| Thermal Resistance, TSSOP | θJA | | 128 | | °C/W | TSSOP | 2 |
| Power Dissipation in Still Air, TSSOP | PD | | | 450 | mW | At 85°C, TSSOP | 2 |
| DC Supply Voltage (Referenced to GND) | VCC | 2 | | 6 | V | | 2 |
| DC Input Voltage, Output Voltage (Referenced to GND) | VIN, VOUT | 0 | | | V | 0 to VCC | 2 |
| Operating Temperature Range, All Package Types | TA | -55 | | 125 | °C | | 2 |
| Input Rise/Fall Time | tr, tf | 0 | | 1000 | ns | VCC = 2.0 V | 2 |
| Input Rise/Fall Time | tr, tf | 0 | | 500 | ns | VCC = 4.5 V | 2 |
| Input Rise/Fall Time | tr, tf | 0 | | 400 | ns | VCC = 6.0 V | 2 |
| Minimum High-Level Input Voltage | VIH | 1.5 | | | V | VCC = 2.0 V; VOUT = 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 |
| Minimum High-Level Input Voltage | VIH | 3.15 | | | V | VCC = 4.5 V; VOUT = 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 |
| Minimum High-Level Input Voltage | VIH | 4.2 | | | V | VCC = 6.0 V; VOUT = 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 |
| Maximum Low-Level Input Voltage | VIL | | | 0.5 | V | VCC = 2.0 V; VOUT = VCC - 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 |
| Maximum Low-Level Input Voltage | VIL | | | 1.35 | V | VCC = 4.5 V; VOUT = VCC - 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 |
| Maximum Low-Level Input Voltage | VIL | | | 1.8 | V | VCC = 6.0 V; VOUT = VCC - 0.1 V, /IOUT/ ≤ 20 µA; all temperature columns | 3 |
| Minimum High-Level Output Voltage | VOH | 4.4 | | | V | VCC = 4.5 V; VIN = VIL, /IOUT/ ≤ 20 µA; all temperature columns | 3 |
| Minimum High-Level Output Voltage | VOH | 3.98 | | | V | VCC = 4.5 V; VIN = VIL, /IOUT/ ≤ 6.0 mA; -55 to 25°C | 3 |
| Minimum High-Level Output Voltage | VOH | 3.84 | | | V | VCC = 4.5 V; VIN = VIL, /IOUT/ ≤ 6.0 mA; ≤85°C | 3 |
| Minimum High-Level Output Voltage | VOH | 3.7 | | | V | VCC = 4.5 V; VIN = VIL, /IOUT/ ≤ 6.0 mA; ≤125°C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.1 | V | VCC = 4.5 V; VIN = VIH, /IOUT/ ≤ 20 µA; all temperature columns | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.26 | V | VCC = 4.5 V; VIN = VIH, /IOUT/ ≤ 6.0 mA; -55 to 25°C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.33 | V | VCC = 4.5 V; VIN = VIH, /IOUT/ ≤ 6.0 mA; ≤85°C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.4 | V | VCC = 4.5 V; VIN = VIH, /IOUT/ ≤ 6.0 mA; ≤125°C | 3 |
| Maximum Input Leakage Current | IIN | -0.1 | | 0.1 | µA | VIN = VCC or GND; VCC = 6.0 V; -55 to 25°C | 3 |
| Maximum Input Leakage Current | IIN | -1 | | 1 | µA | VIN = VCC or GND; VCC = 6.0 V; ≤85°C | 3 |
| Maximum 3-State Leakage Current | IOZ | -0.5 | | 0.5 | µA | Output in high impedance state; VIN = VIL or VIH; VOUT = VCC or GND; VCC = 6.0 V; -55 to 25°C | 3 |
| Maximum 3-State Leakage Current | IOZ | -5 | | 5 | µA | Output in high impedance state; VIN = VIL or VIH; VOUT = VCC or GND; VCC = 6.0 V; ≤85°C | 3 |
| Maximum 3-State Leakage Current | IOZ | -10 | | 10 | µA | Output in high impedance state; VIN = VIL or VIH; VOUT = VCC or GND; VCC = 6.0 V; ≤125°C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 4 | µA | VIN = VCC or GND; IOUT = 0 µA; VCC = 6.0 V; -55 to 25°C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 40 | µA | VIN = VCC or GND; IOUT = 0 µA; VCC = 6.0 V; ≤85°C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 160 | µA | VIN = VCC or GND; IOUT = 0 µA; VCC = 6.0 V; ≤125°C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 18 | ns | VCC = 4.5 V; CL = 50 pF; -55 to 25°C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 23 | ns | VCC = 4.5 V; CL = 50 pF; ≤85°C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 28 | ns | VCC = 4.5 V; CL = 50 pF; ≤125°C | 3 |
| Maximum Propagation Delay, Output Enable to Output Y | tPLZ, tPHZ | | | 25 | ns | VCC = 4.5 V; CL = 50 pF; -55 to 25°C | 3 |
| Maximum Propagation Delay, Output Enable to Output Y | tPLZ, tPHZ | | | 31 | ns | VCC = 4.5 V; CL = 50 pF; ≤85°C | 3 |
| Maximum Propagation Delay, Output Enable to Output Y | tPLZ, tPHZ | | | 38 | ns | VCC = 4.5 V; CL = 50 pF; ≤125°C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 12 | ns | VCC = 4.5 V; CL = 50 pF; -55 to 25°C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 15 | ns | VCC = 4.5 V; CL = 50 pF; ≤85°C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 18 | ns | VCC = 4.5 V; CL = 50 pF; ≤125°C | 3 |
| Maximum Input Capacitance | CIN | | | 10 | pF | All temperature columns | 3 |
| Maximum 3-State Output Capacitance (High Impedance State Output) | COUT | | | 15 | pF | All temperature columns | 3 |
| Power Dissipation Capacitance (Per Buffer) | CPD | | 35 | | pF | Typical @ 25°C, VCC = 5.0 V, VEE = 0 V | 3 |
## CAD (KiCad official)
- Symbol: `MC74HC541ADTG`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `mc74hc541adtg-etched.step` / `mc74hc541adtg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hc541adtg.step` / `mc74hc541adtg.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hc541adt-d.pdf) (8 pp, sha256 `da20b133da2c877c`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hc541adtg-datasheet.pdf)