component
MC74HC4060ADTR2G
Public Made by Adomby adom
onsemi Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HC4060ADTR2G
onsemi · Counters, Dividers · TSSOP-16
MC74HC4060ADTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Active-high counter output that divides the Osc In clock frequency by 2^12 (4096); Q1, Q2, Q3 and Q11 are not available as outputs. |
| 2 | Q13 | output | Active-high counter output that divides the Osc In clock frequency by 2^13 (8192). |
| 3 | Q14 | output | Active-high counter output that divides the Osc In clock frequency by 2^14 (16384), and is driven low by a high level on Reset. |
| 4 | Q6 | output | Active-high counter output that divides the Osc In clock frequency by 2^6 (64). |
| 5 | Q5 | output | Active-high counter output that divides the Osc In clock frequency by 2^5 (32). |
| 6 | Q7 | output | Active-high counter output that divides the Osc In clock frequency by 2^7 (128). |
| 7 | Q4 | output | Active-high counter output that divides the Osc In clock frequency by 2^4 (16). |
| 8 | GND | power_in | Ground reference for the device; all DC voltages and input/output voltages are referenced to this pin. |
| 9 | Osc Out 2 | output | Oscillator output used with Osc In and external components to form the oscillator; it must be left open-circuited when Osc In is driven by an external clock, and in the crystal configuration described in the text. |
| 10 | Osc Out 1 | output | Oscillator output used with Osc In and external components to form the oscillator; it must be left open-circuited when Osc In is driven by an external clock source. |
| 11 | Osc In | input | Negative-edge triggered clock input that advances the counter on each high-to-low transition and may be driven by an external clock source. |
| 12 | Reset | input | Active-high asynchronous reset that forces the counter to zero (all Q outputs low) and disables the oscillator. |
| 13 | Q9 | output | Active-high counter output that divides the Osc In clock frequency by 2^9 (512). |
| 14 | Q8 | output | Active-high counter output that divides the Osc In clock frequency by 2^8 (256). |
| 15 | Q10 | output | Active-high counter output that divides the Osc In clock frequency by 2^10 (1024). |
| 16 | VCC | power_in | Positive supply pin; recommended DC supply range is 2.5 V to 6.0 V referenced to GND (absolute maximum −0.5 V to +7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| DC Input Voltage (Referenced to GND), max printed as VCC + 0.5 | Vin | -0.5 | V | Referenced to GND; max printed as VCC + 0.5 V | 2 | ||
| DC Output Voltage (Referenced to GND), max printed as VCC + 0.5 | Vout | -0.5 | V | Referenced to GND; max printed as VCC + 0.5 V | 2 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | Per pin | 2 | |
| DC Output Current, per Pin | Iout | -25 | 25 | mA | Per pin | 2 | |
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | VCC and GND pins | 2 | |
| Power Dissipation in Still Air, TSSOP Package | PD | 450 | mW | Still air; derate -6.1 mW/°C from 65 to 125°C | 2 | ||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 2 | ||
| Lead Temperature, TSSOP Package | TL | 260 | °C | 1 mm from case for 10 seconds | 2 | ||
| DC Supply Voltage (Referenced to GND) | VCC | 2.5 | 6 | V | Referenced to GND; oscillator guaranteed at 2.5 V minimum, parametrics tested at 2.0 V | 2 | |
| DC Input Voltage, Output Voltage (Referenced to GND), max printed as VCC | Vin, Vout | 0 | V | Referenced to GND; max printed as VCC | 2 | ||
| Operating Temperature Range, All Package Types | TA | -55 | 125 | °C | 2 | ||
| Input Rise/Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V (Figure 1) | 2 | |
| Input Rise/Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V (Figure 1) | 2 | |
| Input Rise/Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V (Figure 1) | 2 | |
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V; Vout = 0.1V or VCC -0.1V; /Iout/ ≤ 20 µA | 2 | ||
| Minimum High-Level Input Voltage | VIH | 2.1 | V | VCC = 3.0 V; Vout = 0.1V or VCC -0.1V; /Iout/ ≤ 20 µA | 2 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC = 4.5 V; Vout = 0.1V or VCC -0.1V; /Iout/ ≤ 20 µA | 2 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | VCC = 6.0 V; Vout = 0.1V or VCC -0.1V; /Iout/ ≤ 20 µA | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC = 2.0 V; Vout = 0.1V or VCC -0.1V; /Iout/ ≤ 20 µA | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | VCC = 3.0 V; Vout = 0.1V or VCC -0.1V; /Iout/ ≤ 20 µA | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | VCC = 4.5 V; Vout = 0.1V or VCC -0.1V; /Iout/ ≤ 20 µA | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | VCC = 6.0 V; Vout = 0.1V or VCC -0.1V; /Iout/ ≤ 20 µA | 2 | ||
| Minimum High-Level Output Voltage (Q4-Q10, Q12-Q14) | VOH | 1.9 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 2 | ||
| Minimum High-Level Output Voltage (Q4-Q10, Q12-Q14) | VOH | 4.4 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 2 | ||
| Minimum High-Level Output Voltage (Q4-Q10, Q12-Q14) | VOH | 5.9 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 2 | ||
| Minimum High-Level Output Voltage (Q4-Q10, Q12-Q14) | VOH | 2.2 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA | 2 | ||
| Minimum High-Level Output Voltage (Q4-Q10, Q12-Q14) | VOH | 3.7 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA | 2 | ||
| Minimum High-Level Output Voltage (Q4-Q10, Q12-Q14) | VOH | 5.2 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA | 2 | ||
| Maximum Low-Level Output Voltage (Q4-Q10, Q12-Q14) | VOL | 0.1 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 2 | ||
| Maximum Low-Level Output Voltage (Q4-Q10, Q12-Q14) | VOL | 0.4 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA | 2 | ||
| Minimum High-Level Output Voltage (Osc Out 1, Osc Out 2) | VOH | 2.2 | V | VCC = 3.0 V; Vin = VCC or GND; /Iout/ ≤ 0.7 mA | 3 | ||
| Minimum High-Level Output Voltage (Osc Out 1, Osc Out 2) | VOH | 3.7 | V | VCC = 4.5 V; Vin = VCC or GND; /Iout/ ≤ 1.0 mA | 3 | ||
| Minimum High-Level Output Voltage (Osc Out 1, Osc Out 2) | VOH | 5.2 | V | VCC = 6.0 V; Vin = VCC or GND; /Iout/ ≤ 1.3 mA | 3 | ||
| Maximum Low-Level Output Voltage (Osc Out 1, Osc Out 2) | VOL | 0.4 | V | VCC = 3.0 V; Vin = VCC or GND; /Iout/ ≤ 0.7 mA | 3 | ||
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | VCC = 6.0 V; Vin = VCC or GND | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | µA | VCC = 6.0 V; Vin = VCC or GND; Iout = 0 A | 3 | ||
| Maximum Clock Frequency (50% Duty Cycle), guaranteed minimum | fmax | 8 | MHz | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Clock Frequency (50% Duty Cycle), guaranteed minimum | fmax | 12 | MHz | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Clock Frequency (50% Duty Cycle), guaranteed minimum | fmax | 25 | MHz | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Clock Frequency (50% Duty Cycle), guaranteed minimum | fmax | 40 | MHz | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Osc In to Q4 | tPLH, tPHL | 450 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Osc In to Q4 | tPLH, tPHL | 250 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Osc In to Q4 | tPLH, tPHL | 90 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Osc In to Q4 | tPLH, tPHL | 75 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Reset to Any Q | tPHL | 300 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Reset to Any Q | tPHL | 125 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Reset to Any Q | tPHL | 61 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Reset to Any Q | tPHL | 53 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Qn to Qn+1 | tPLH, tPHL | 125 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Qn to Qn+1 | tPLH, tPHL | 95 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Qn to Qn+1 | tPLH, tPHL | 24 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Propagation Delay, Qn to Qn+1 | tPLH, tPHL | 20 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns | 3 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 3 |
CAD (KiCad official)
- Symbol:
MC74HC4060ADTR2G - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hc4060adtr2g-etched.step/mc74hc4060adtr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc4060adtr2g.step/mc74hc4060adtr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (11 pp, sha256
5c50a6db07194f2b, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).