component
MC74HC4053ADTR2G
Public Made by Adomby adom
onsemi Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MC74HC4053ADTR2G
onsemi · Analog Switches, Multiplexers · TSSOP-16
MC74HC4053ADTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | passive | Analog input/output channel Y1 of the Y switch, which is connected to the Y common pin when selected by input B. |
| 2 | Y0 | passive | Analog input/output channel Y0 of the Y switch, which is connected to the Y common pin when selected by input B. |
| 3 | Z1 | passive | Analog input/output channel Z1 of the Z switch, which is connected to the Z common pin when selected by input C; analog voltages must stay between VEE and VCC. |
| 4 | Z | passive | Common analog output/input of the Z switch, selected between Z0 and Z1 by channel-select input C. |
| 5 | Z0 | passive | Analog input/output channel Z0 of the Z switch, which is connected to the Z common pin when selected by input C; analog voltages must stay between VEE and VCC. |
| 6 | ENABLE | input | Active-high enable; when HIGH all analog switches are turned off, and the input must be held at VCC or GND logic levels. |
| 7 | VEE | power_in | Negative DC supply for the analog switches, with VEE − GND = 0 to −6.0 V and VEE ≤ GND. |
| 8 | GND | power_in | Ground reference for the digital control logic, with VCC − GND = 2.0 to 6.0 V. |
| 9 | C | input | Channel-select input that chooses the Z switch channel (Z0 or Z1); it must be at VCC or GND logic levels. |
| 10 | B | input | Channel-select input that chooses the Y switch channel (Y0 or Y1); it must be at VCC or GND logic levels. |
| 11 | A | input | Channel-select input that chooses the X switch channel (X0 or X1); it must be at VCC or GND logic levels. |
| 12 | X0 | passive | Analog input/output channel X0 of the X switch, which is connected to the X common pin when selected by input A. |
| 13 | X1 | passive | Analog input/output channel X1 of the X switch, which is connected to the X common pin when selected by input A. |
| 14 | X | passive | Common analog output/input of the X switch, selected between X0 and X1 by channel-select input A. |
| 15 | Y | passive | Common analog output/input of the Y switch, selected between Y0 and Y1 by channel-select input B. |
| 16 | VCC | power_in | Positive DC supply, with VCC − GND = 2.0 to 6.0 V for digital control and VCC − VEE = 2.0 to 12.0 V for the analog range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive DC Supply Voltage (referenced to GND) | VCC | 2 | 6 | V | Referenced to GND | 4 | |
| Positive DC Supply Voltage (referenced to VEE) | VCC | 2 | 12 | V | Referenced to VEE | 4 | |
| Negative DC Supply Voltage, Output (referenced to GND) | VEE | -6 | V | Referenced to GND; printed max is GND | 4 | ||
| Static or Dynamic Voltage Across Switch | VIO | 1.2 | V | 4 | |||
| Operating Temperature Range, All Package Types | TA | -55 | 125 | °C | 4 | ||
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | 1000 | ns | VCC = 2.0 V | 4 | |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | 600 | ns | VCC = 3.0 V | 4 | |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | 500 | ns | VCC = 4.5 V | 4 | |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | 400 | ns | VCC = 6.0 V | 4 | |
| Positive DC Supply Voltage (referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 3 | |
| Positive DC Supply Voltage (referenced to VEE) | VCC | -0.5 | 14 | V | Referenced to VEE | 3 | |
| Negative DC Supply Voltage (referenced to GND) | VEE | -7 | 5 | V | Referenced to GND | 3 | |
| Digital Input Voltage (referenced to GND) | Vin | -0.5 | V | Referenced to GND; printed max is VCC + 0.5 | 3 | ||
| DC Current, Into or Out of Any Pin | I | -25 | 25 | mA | 3 | ||
| Power Dissipation in Still Air, TSSOP Package | PD | 450 | mW | Still air, TSSOP package | 3 | ||
| TSSOP Package Derating | -6.1 | mW/C | From 65 to 125 °C, TSSOP package | 3 | |||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 3 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds, SOIC or TSSOP package | 3 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 1.5 | V | Ron = Per Spec; VCC = 2.0 V; column ≤125 °C | 4 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 2.1 | V | Ron = Per Spec; VCC = 3.0 V; column ≤125 °C | 4 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 3.15 | V | Ron = Per Spec; VCC = 4.5 V; column ≤125 °C | 4 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 4.2 | V | Ron = Per Spec; VCC = 6.0 V; column ≤125 °C | 4 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 0.5 | V | Ron = Per Spec; VCC = 2.0 V; column ≤125 °C | 4 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 0.9 | V | Ron = Per Spec; VCC = 3.0 V; column ≤125 °C | 4 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 1.35 | V | Ron = Per Spec; VCC = 4.5 V; column ≤125 °C | 4 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 1.8 | V | Ron = Per Spec; VCC = 6.0 V; column ≤125 °C | 4 | ||
| Maximum Input Leakage Current, Channel-Select or Enable Inputs | Iin | -1 | 1 | µA | Vin = VCC or GND, VEE = -6.0 V; VCC = 6.0 V; column ≤125 °C | 4 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 10 | µA | Channel Select, Enable and VIS = VCC or GND; VEE = GND; VIO = 0 V; VCC = 6.0 V; column ≤125 °C | 4 | ||
| Maximum ON Resistance | Ron | 280 | Ω | Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; VCC = 4.5 V, VEE = 0.0 V; column ≤125 °C | 5 | ||
| Maximum ON Resistance | Ron | 170 | Ω | Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; VCC = 4.5 V, VEE = -4.5 V; column ≤125 °C | 5 | ||
| Maximum ON Resistance | Ron | 140 | Ω | Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 | ||
| Maximum ON Resistance (endpoints) | Ron | 230 | Ω | Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; VCC = 4.5 V, VEE = 0.0 V; column ≤125 °C | 5 | ||
| Maximum ON Resistance (endpoints) | Ron | 140 | Ω | Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; VCC = 4.5 V, VEE = -4.5 V; column ≤125 °C | 5 | ||
| Maximum ON Resistance (endpoints) | Ron | 115 | Ω | Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 | ||
| Maximum Ron Difference Between Any Two Channels in the Same Package | Ron | 40 | Ω | Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; VCC = 4.5 V, VEE = 0.0 V; column ≤125 °C | 5 | ||
| Maximum Ron Difference Between Any Two Channels in the Same Package | Ron | 18 | Ω | Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; VCC = 4.5 V, VEE = -4.5 V; column ≤125 °C | 5 | ||
| Maximum Ron Difference Between Any Two Channels in the Same Package | Ron | 14 | Ω | Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 | ||
| Maximum Off-Channel Leakage Current, Any One Channel | Ioff | 1 | µA | Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 3); VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 | ||
| Maximum Off-Channel Leakage Current, Common Channel (HC4053A) | Ioff | 2 | µA | Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 4); VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 | ||
| Maximum On-Channel Leakage Current, Channel-to-Channel (HC4053A) | Ion | 2 | µA | Vin = VIL or VIH; Switch-to-Switch = VCC − VEE (Figure 5); VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | 350 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 2.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | 125 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 3.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | 85 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 4.5 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | 75 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 6.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | 70 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 2.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | 32 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 3.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | 18 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 4.5 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | 15 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 6.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Enable to Analog Output (turn-off) | tPLZ, tPHZ | 220 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 2.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Enable to Analog Output (turn-off) | tPLZ, tPHZ | 110 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 3.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Enable to Analog Output (turn-off) | tPLZ, tPHZ | 76 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 4.5 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Enable to Analog Output (turn-off) | tPLZ, tPHZ | 63 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 6.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Enable to Analog Output (turn-on) | tPZL, tPZH | 345 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 2.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Enable to Analog Output (turn-on) | tPZL, tPZH | 155 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 3.0 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Enable to Analog Output (turn-on) | tPZL, tPZH | 83 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 4.5 V; column ≤125 °C | 5 | ||
| Maximum Propagation Delay, Enable to Analog Output (turn-on) | tPZL, tPZH | 67 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 6.0 V; column ≤125 °C | 5 | ||
| Maximum Input Capacitance, Channel-Select or Enable Inputs | Cin | 10 | pF | 5 | |||
| Maximum Capacitance Analog I/O (All Switches Off) | CI/O | 35 | pF | All switches off | 5 | ||
| Maximum Capacitance Common O/I (HC4053A) | CI/O | 50 | pF | All switches off | 5 |
CAD (KiCad official)
- Symbol:
MC74HC4053ADTR2G - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hc4053adtr2g-etched.step/mc74hc4053adtr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc4053adtr2g.step/mc74hc4053adtr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (17 pp, sha256
a6f0761b992c3b16, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HC4053ADTR2G
**onsemi** · Analog Switches, Multiplexers · TSSOP-16
MC74HC4053ADTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | passive | Analog input/output channel Y1 of the Y switch, which is connected to the Y common pin when selected by input B. |
| 2 | Y0 | passive | Analog input/output channel Y0 of the Y switch, which is connected to the Y common pin when selected by input B. |
| 3 | Z1 | passive | Analog input/output channel Z1 of the Z switch, which is connected to the Z common pin when selected by input C; analog voltages must stay between VEE and VCC. |
| 4 | Z | passive | Common analog output/input of the Z switch, selected between Z0 and Z1 by channel-select input C. |
| 5 | Z0 | passive | Analog input/output channel Z0 of the Z switch, which is connected to the Z common pin when selected by input C; analog voltages must stay between VEE and VCC. |
| 6 | ENABLE | input | Active-high enable; when HIGH all analog switches are turned off, and the input must be held at VCC or GND logic levels. |
| 7 | VEE | power_in | Negative DC supply for the analog switches, with VEE − GND = 0 to −6.0 V and VEE ≤ GND. |
| 8 | GND | power_in | Ground reference for the digital control logic, with VCC − GND = 2.0 to 6.0 V. |
| 9 | C | input | Channel-select input that chooses the Z switch channel (Z0 or Z1); it must be at VCC or GND logic levels. |
| 10 | B | input | Channel-select input that chooses the Y switch channel (Y0 or Y1); it must be at VCC or GND logic levels. |
| 11 | A | input | Channel-select input that chooses the X switch channel (X0 or X1); it must be at VCC or GND logic levels. |
| 12 | X0 | passive | Analog input/output channel X0 of the X switch, which is connected to the X common pin when selected by input A. |
| 13 | X1 | passive | Analog input/output channel X1 of the X switch, which is connected to the X common pin when selected by input A. |
| 14 | X | passive | Common analog output/input of the X switch, selected between X0 and X1 by channel-select input A. |
| 15 | Y | passive | Common analog output/input of the Y switch, selected between Y0 and Y1 by channel-select input B. |
| 16 | VCC | power_in | Positive DC supply, with VCC − GND = 2.0 to 6.0 V for digital control and VCC − VEE = 2.0 to 12.0 V for the analog range. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive DC Supply Voltage (referenced to GND) | VCC | 2 | | 6 | V | Referenced to GND | 4 |
| Positive DC Supply Voltage (referenced to VEE) | VCC | 2 | | 12 | V | Referenced to VEE | 4 |
| Negative DC Supply Voltage, Output (referenced to GND) | VEE | -6 | | | V | Referenced to GND; printed max is GND | 4 |
| Static or Dynamic Voltage Across Switch | VIO | | | 1.2 | V | | 4 |
| Operating Temperature Range, All Package Types | TA | -55 | | 125 | °C | | 4 |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | | 1000 | ns | VCC = 2.0 V | 4 |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | | 600 | ns | VCC = 3.0 V | 4 |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | | 500 | ns | VCC = 4.5 V | 4 |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | | 400 | ns | VCC = 6.0 V | 4 |
| Positive DC Supply Voltage (referenced to GND) | VCC | -0.5 | | 7 | V | Referenced to GND | 3 |
| Positive DC Supply Voltage (referenced to VEE) | VCC | -0.5 | | 14 | V | Referenced to VEE | 3 |
| Negative DC Supply Voltage (referenced to GND) | VEE | -7 | | 5 | V | Referenced to GND | 3 |
| Digital Input Voltage (referenced to GND) | Vin | -0.5 | | | V | Referenced to GND; printed max is VCC + 0.5 | 3 |
| DC Current, Into or Out of Any Pin | I | -25 | | 25 | mA | | 3 |
| Power Dissipation in Still Air, TSSOP Package | PD | | | 450 | mW | Still air, TSSOP package | 3 |
| TSSOP Package Derating | | | -6.1 | | mW/C | From 65 to 125 °C, TSSOP package | 3 |
| Storage Temperature Range | Tstg | -65 | | 150 | °C | | 3 |
| Lead Temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds, SOIC or TSSOP package | 3 |
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 1.5 | | | V | Ron = Per Spec; VCC = 2.0 V; column ≤125 °C | 4 |
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 2.1 | | | V | Ron = Per Spec; VCC = 3.0 V; column ≤125 °C | 4 |
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 3.15 | | | V | Ron = Per Spec; VCC = 4.5 V; column ≤125 °C | 4 |
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 4.2 | | | V | Ron = Per Spec; VCC = 6.0 V; column ≤125 °C | 4 |
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 0.5 | V | Ron = Per Spec; VCC = 2.0 V; column ≤125 °C | 4 |
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 0.9 | V | Ron = Per Spec; VCC = 3.0 V; column ≤125 °C | 4 |
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 1.35 | V | Ron = Per Spec; VCC = 4.5 V; column ≤125 °C | 4 |
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 1.8 | V | Ron = Per Spec; VCC = 6.0 V; column ≤125 °C | 4 |
| Maximum Input Leakage Current, Channel-Select or Enable Inputs | Iin | -1 | | 1 | µA | Vin = VCC or GND, VEE = -6.0 V; VCC = 6.0 V; column ≤125 °C | 4 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 10 | µA | Channel Select, Enable and VIS = VCC or GND; VEE = GND; VIO = 0 V; VCC = 6.0 V; column ≤125 °C | 4 |
| Maximum ON Resistance | Ron | | | 280 | Ω | Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; VCC = 4.5 V, VEE = 0.0 V; column ≤125 °C | 5 |
| Maximum ON Resistance | Ron | | | 170 | Ω | Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; VCC = 4.5 V, VEE = -4.5 V; column ≤125 °C | 5 |
| Maximum ON Resistance | Ron | | | 140 | Ω | Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 |
| Maximum ON Resistance (endpoints) | Ron | | | 230 | Ω | Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; VCC = 4.5 V, VEE = 0.0 V; column ≤125 °C | 5 |
| Maximum ON Resistance (endpoints) | Ron | | | 140 | Ω | Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; VCC = 4.5 V, VEE = -4.5 V; column ≤125 °C | 5 |
| Maximum ON Resistance (endpoints) | Ron | | | 115 | Ω | Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 |
| Maximum Ron Difference Between Any Two Channels in the Same Package | Ron | | | 40 | Ω | Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; VCC = 4.5 V, VEE = 0.0 V; column ≤125 °C | 5 |
| Maximum Ron Difference Between Any Two Channels in the Same Package | Ron | | | 18 | Ω | Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; VCC = 4.5 V, VEE = -4.5 V; column ≤125 °C | 5 |
| Maximum Ron Difference Between Any Two Channels in the Same Package | Ron | | | 14 | Ω | Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 |
| Maximum Off-Channel Leakage Current, Any One Channel | Ioff | | | 1 | µA | Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 3); VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 |
| Maximum Off-Channel Leakage Current, Common Channel (HC4053A) | Ioff | | | 2 | µA | Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 4); VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 |
| Maximum On-Channel Leakage Current, Channel-to-Channel (HC4053A) | Ion | | | 2 | µA | Vin = VIL or VIH; Switch-to-Switch = VCC − VEE (Figure 5); VCC = 6.0 V, VEE = -6.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | | | 350 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 2.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | | | 125 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 3.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | | | 85 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 4.5 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | | | 75 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 6.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | | | 70 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 2.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | | | 32 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 3.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | | | 18 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 4.5 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | | | 15 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 6.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Enable to Analog Output (turn-off) | tPLZ, tPHZ | | | 220 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 2.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Enable to Analog Output (turn-off) | tPLZ, tPHZ | | | 110 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 3.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Enable to Analog Output (turn-off) | tPLZ, tPHZ | | | 76 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 4.5 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Enable to Analog Output (turn-off) | tPLZ, tPHZ | | | 63 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 6.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Enable to Analog Output (turn-on) | tPZL, tPZH | | | 345 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 2.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Enable to Analog Output (turn-on) | tPZL, tPZH | | | 155 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 3.0 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Enable to Analog Output (turn-on) | tPZL, tPZH | | | 83 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 4.5 V; column ≤125 °C | 5 |
| Maximum Propagation Delay, Enable to Analog Output (turn-on) | tPZL, tPZH | | | 67 | ns | CL = 50 pF, Input tr = tf = 6 ns; VCC = 6.0 V; column ≤125 °C | 5 |
| Maximum Input Capacitance, Channel-Select or Enable Inputs | Cin | | | 10 | pF | | 5 |
| Maximum Capacitance Analog I/O (All Switches Off) | CI/O | | | 35 | pF | All switches off | 5 |
| Maximum Capacitance Common O/I (HC4053A) | CI/O | | | 50 | pF | All switches off | 5 |
## CAD (KiCad official)
- Symbol: `MC74HC4053ADTR2G`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `mc74hc4053adtr2g-etched.step` / `mc74hc4053adtr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hc4053adtr2g.step` / `mc74hc4053adtr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hc4053adtr2-d.pdf) (17 pp, sha256 `a6f0761b992c3b16`, retrieved 2026-10-21, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hc4053adtr2g-datasheet.pdf)