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MC74HC251ADTR2G

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onsemi Signal Switches, Multiplexers, Decoders, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74HC251ADTR2G

onsemi · Signal Switches, Multiplexers, Decoders · TSSOP-16

MC74HC251ADTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D3 input Data input D3 is one of eight binary data inputs selected by the address inputs to appear at the outputs when Output Enable is low.
2 D2 input Data input D2 is one of eight binary data inputs selected by the address inputs to appear at the outputs when Output Enable is low.
3 D1 input Data input D1 is one of eight binary data inputs selected by the address inputs to appear at the outputs when Output Enable is low.
4 D0 input Data input D0 is one of eight binary data inputs selected by the address inputs to appear at the outputs when Output Enable is low.
5 Y output True data output Y presents the selected data input and goes to high impedance when Output Enable is high.
6 Y̅ output Complemented data output Y̅ presents the inverted selected data input and goes to high impedance when Output Enable is high.
7 OUTPUT ENABLE input Output Enable must be held low for the selected data to appear at the outputs, and a high level forces both Y and Y̅ into the high-impedance state.
8 GND power_in Ground reference pin for the device, with all voltages referenced to GND.
9 A2 input Address input A2 is the most significant bit of the binary address that selects one of the eight data inputs.
10 A1 input Address input A1 is the middle bit of the binary address that selects one of the eight data inputs.
11 A0 input Address input A0 is the least significant bit of the binary address that selects one of the eight data inputs.
12 D7 input Data input D7 is one of eight binary data inputs selected by the address inputs to appear at the outputs when Output Enable is low.
13 D6 input Data input D6 is one of eight binary data inputs selected by the address inputs to appear at the outputs when Output Enable is low.
14 D5 input Data input D5 is one of eight binary data inputs selected by the address inputs to appear at the outputs when Output Enable is low.
15 D4 input Data input D4 is one of eight binary data inputs selected by the address inputs to appear at the outputs when Output Enable is low.
16 VCC power_in Positive supply pin, with the device specified for a DC supply voltage of 2.0 V to 6.0 V referenced to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage (Referenced to GND) VCC -0.5 7 V Referenced to GND 2
DC Input Voltage (Referenced to GND) Vin -1.5 V Max = VCC + 1.5 V, referenced to GND 2
DC Output Voltage (Referenced to GND) Vout -0.5 V Max = VCC + 0.5 V, referenced to GND 2
DC Input Current, per Pin Iin -25 25 mA Per pin 2
DC Output Current, per Pin Iout -50 50 mA Per pin 2
DC Supply Current, VCC and GND Pins ICC -75 75 mA VCC and GND pins 2
Storage Temperature Tstg -65 150 °C 2
DC Supply Voltage (Referenced to GND) VCC 2 6 V Referenced to GND 2
DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout 0 V Max = VCC, referenced to GND 2
Operating Temperature, All Package Types TA -55 125 °C All package types 2
Input Rise and Fall Time tr, tf 0 1000 ns VCC = 2.0 V (Figure 2) 2
Input Rise and Fall Time tr, tf 0 500 ns VCC = 4.5 V 2
Input Rise and Fall Time tr, tf 0 400 ns VCC = 6.0 V 2
Minimum High-Level Input Voltage VIH 1.5 V VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; 125 °C column 3
Minimum High-Level Input Voltage VIH 3.15 V VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; 125 °C column 3
Minimum High-Level Input Voltage VIH 4.2 V VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; 125 °C column 3
Maximum Low-Level Input Voltage VIL 0.3 V VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; 125 °C column 3
Maximum Low-Level Input Voltage VIL 0.9 V VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; 125 °C column 3
Maximum Low-Level Input Voltage VIL 1.2 V VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; 125 °C column 3
Minimum High-Level Output Voltage VOH 1.9 V VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA 3
Minimum High-Level Output Voltage VOH 4.4 V VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA 3
Minimum High-Level Output Voltage VOH 5.9 V VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA 3
Minimum High-Level Output Voltage VOH 3.7 V VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; 125 °C column 3
Minimum High-Level Output Voltage VOH 5.2 V VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; 125 °C column 3
Maximum Low-Level Output Voltage VOL 0.1 V VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA 3
Maximum Low-Level Output Voltage VOL 0.4 V VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; 125 °C column 3
Maximum Input Leakage Current Iin -1 1 A VCC = 6.0 V; Vin = VCC or GND; 125 °C column 3
Maximum Three-State Leakage Current IOZ -10 10 A VCC = 6.0 V; output in high-impedance state; Vin = VIL or VIH; Vout = VCC or GND; 125 °C column 3
Maximum Quiescent Supply Current (per Package) ICC 160 A VCC = 6.0 V; Vin = VCC or GND; Iout = 0 A; 125 °C column 3
Maximum Propagation Delay, Input D to Output Y or Y tPLH, tPHL 280 ns VCC = 2.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Input D to Output Y or Y tPLH, tPHL 56 ns VCC = 4.5 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Input D to Output Y or Y tPLH, tPHL 48 ns VCC = 6.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Input A to Output Y or Y tPLH, tPHL 310 ns VCC = 2.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Input A to Output Y or Y tPLH, tPHL 62 ns VCC = 4.5 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Input A to Output Y or Y tPLH, tPHL 53 ns VCC = 6.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPLZ, tPHZ 295 ns VCC = 2.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPLZ, tPHZ 59 ns VCC = 4.5 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPLZ, tPHZ 50 ns VCC = 6.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPZL, tPZH 220 ns VCC = 2.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPZL, tPZH 44 ns VCC = 4.5 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPZL, tPZH 38 ns VCC = 6.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPLZ, tPHZ 330 ns VCC = 2.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPLZ, tPHZ 66 ns VCC = 4.5 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPLZ, tPHZ 56 ns VCC = 6.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPZL, tPZH 225 ns VCC = 2.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Propagation Delay, Output Enable to Output Y tPZL, tPZH 45 ns VCC = 4.5 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Output Transition Time, Any Output tTLH, tTHL 110 ns VCC = 2.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Output Transition Time, Any Output tTLH, tTHL 22 ns VCC = 4.5 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Output Transition Time, Any Output tTLH, tTHL 19 ns VCC = 6.0 V; CL = 50 pF; Input tr = tf = 6 ns; 125 °C column 4
Maximum Input Capacitance Cin 10 pF 4
Maximum Three-State Output Capacitance Cout 15 pF Output in high-impedance state 4
Power Dissipation Capacitance (Per Package) CPD 36 pF Typical @ 25°C, VCC = 5.0 V 4

CAD (KiCad official)

  • Symbol: MC74HC251ADTR2G
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: mc74hc251adtr2g-etched.step / mc74hc251adtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hc251adtr2g.step / mc74hc251adtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 7299a178753bd5db, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF