component
MC74HC175ADG
Public Made by Adomby adom
onsemi Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MC74HC175ADG
onsemi · Flip Flops · SOIC-16
MC74HC175ADG from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | input | Active-low asynchronous reset input; a low level applied here resets the flip-flops independently of the clock. |
| 2 | Q0 | output | True (non-inverted) output of flip-flop 0, which follows D0 on the next positive-going clock edge; the device drives 10 LSTTL loads. |
| 3 | ~{Q0} | output | Inverted complementary output of flip-flop 0. |
| 4 | D0 | input | Data input of flip-flop 0, transferred to Q0 on the positive-going clock edge; inputs must stay between GND and VCC. |
| 5 | D1 | input | Data input of flip-flop 1, transferred to Q1 on the positive-going clock edge; inputs must stay between GND and VCC. |
| 6 | ~{Q1} | output | Inverted complementary output of flip-flop 1. |
| 7 | Q1 | output | True (non-inverted) output of flip-flop 1, which follows D1 on the next positive-going clock edge. |
| 8 | GND | power_in | Ground reference for all voltages; the datasheet references VIN, VOUT and VCC to GND. |
| 9 | CLOCK | input | Common clock input shared by all four flip-flops; data is latched on the positive-going edge. |
| 10 | Q2 | output | True (non-inverted) output of flip-flop 2, which follows D2 on the next positive-going clock edge. |
| 11 | ~{Q2} | output | Inverted complementary output of flip-flop 2. |
| 12 | D2 | input | Data input of flip-flop 2, transferred to Q2 on the positive-going clock edge; inputs must stay between GND and VCC. |
| 13 | D3 | input | Data input of flip-flop 3, transferred to Q3 on the positive-going clock edge; inputs must stay between GND and VCC. |
| 14 | ~{Q3} | output | Inverted complementary output of flip-flop 3. |
| 15 | Q3 | output | True (non-inverted) output of flip-flop 3, which follows D3 on the next positive-going clock edge. |
| 16 | VCC | power_in | Positive supply pin; the recommended operating supply range is 2.0 V to 6.0 V referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage | VCC | -0.5 | 7 | V | Referenced to GND | 3 | |
| DC input voltage | Vin | -0.5 | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 3 | ||
| DC output voltage | Vout | -0.5 | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 3 | ||
| DC input current, per pin | Iin | -20 | 20 | mA | Per pin | 3 | |
| DC output current, per pin | Iout | -25 | 25 | mA | Per pin | 3 | |
| DC supply current, VCC and GND pins | ICC | -50 | 50 | mA | VCC and GND pins | 3 | |
| Power dissipation in still air | PD | 500 | mW | Still air, SOIC package | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Lead temperature | TL | 260 | °C | 1 mm from case for 10 seconds (plastic DIP, SOIC or TSSOP package) | 3 | ||
| Power dissipation derating | -7 | mW/°C | SOIC package, derate from 65 to 125 °C | 3 | |||
| DC supply voltage | VCC | 2 | 6 | V | Referenced to GND | 3 | |
| DC input and output voltage | Vin, Vout | 0 | V | Referenced to GND; upper limit printed as VCC | 3 | ||
| Operating temperature, all package types | TA | -55 | 125 | °C | 3 | ||
| Input rise and fall time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V (Figure 1) | 3 | |
| Input rise and fall time | tr, tf | 0 | 600 | ns | VCC = 3.0 V (Figure 1) | 3 | |
| Input rise and fall time | tr, tf | 0 | 500 | ns | VCC = 4.5 V (Figure 1) | 3 | |
| Input rise and fall time | tr, tf | 0 | 400 | ns | VCC = 6.0 V (Figure 1) | 3 | |
| Minimum high-level input voltage | VIH | 1.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Minimum high-level input voltage | VIH | 2.1 | V | VCC = 3.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Minimum high-level input voltage | VIH | 3.15 | V | VCC = 4.5 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Minimum high-level input voltage | VIH | 4.2 | V | VCC = 6.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Maximum low-level input voltage | VIL | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Maximum low-level input voltage | VIL | 0.9 | V | VCC = 3.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Maximum low-level input voltage | VIL | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Maximum low-level input voltage | VIL | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Minimum high-level output voltage | VOH | 1.9 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Minimum high-level output voltage | VOH | 4.4 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Minimum high-level output voltage | VOH | 5.9 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Minimum high-level output voltage | VOH | 2.2 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; limit at 125 °C | 4 | ||
| Minimum high-level output voltage | VOH | 3.7 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; limit at 125 °C | 4 | ||
| Minimum high-level output voltage | VOH | 5.2 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; limit at 125 °C | 4 | ||
| Maximum low-level output voltage | VOL | 0.1 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 | ||
| Maximum low-level output voltage | VOL | 0.4 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; limit at 125 °C | 4 | ||
| Maximum input leakage current | Iin | -1 | 1 | µA | VCC = 6.0 V; Vin = VCC or GND; limit at 125 °C | 4 | |
| Maximum quiescent supply current (per package) | ICC | 160 | µA | VCC = 6.0 V; Vin = VCC or GND; Iout = 0 µA; limit at 125 °C | 4 | ||
| Maximum clock frequency (50% duty cycle) | fmax | 4 | MHz | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum clock frequency (50% duty cycle) | fmax | 6 | MHz | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum clock frequency (50% duty cycle) | fmax | 20 | MHz | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum clock frequency (50% duty cycle) | fmax | 24 | MHz | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum propagation delay, clock to Q or Q̅ | tPLH, tPHL | 225 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum propagation delay, clock to Q or Q̅ | tPLH, tPHL | 110 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum propagation delay, clock to Q or Q̅ | tPLH, tPHL | 38 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum propagation delay, clock to Q or Q̅ | tPLH, tPHL | 33 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum propagation delay, reset to Q or Q̅ | tPHL | 190 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum propagation delay, reset to Q or Q̅ | tPHL | 110 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum propagation delay, reset to Q or Q̅ | tPHL | 34 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum propagation delay, reset to Q or Q̅ | tPHL | 30 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum output transition time, any output | tTLH, tTHL | 110 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum output transition time, any output | tTLH, tTHL | 36 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum output transition time, any output | tTLH, tTHL | 22 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum output transition time, any output | tTLH, tTHL | 19 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Maximum input capacitance | Cin | 10 | pF | 5 | |||
| Minimum setup time, data to clock | tsu | 150 | ns | VCC = 2.0 V; Figure 3; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Minimum setup time, data to clock | tsu | 85 | ns | VCC = 3.0 V; Figure 3; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Minimum setup time, data to clock | tsu | 30 | ns | VCC = 4.5 V; Figure 3; input tr = tf = 6 ns; limit at 125 °C | 5 | ||
| Minimum setup time, data to clock | tsu | 26 | ns | VCC = 6.0 V; Figure 3; input tr = tf = 6 ns; limit at 125 °C | 5 |
CAD (KiCad official)
- Symbol:
MC74HC175ADG - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hc175adg-etched.step/mc74hc175adg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc175adg.step/mc74hc175adg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (10 pp, sha256
b9d415769bbcaf08, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HC175ADG
**onsemi** · Flip Flops · SOIC-16
MC74HC175ADG from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | input | Active-low asynchronous reset input; a low level applied here resets the flip-flops independently of the clock. |
| 2 | Q0 | output | True (non-inverted) output of flip-flop 0, which follows D0 on the next positive-going clock edge; the device drives 10 LSTTL loads. |
| 3 | ~{Q0} | output | Inverted complementary output of flip-flop 0. |
| 4 | D0 | input | Data input of flip-flop 0, transferred to Q0 on the positive-going clock edge; inputs must stay between GND and VCC. |
| 5 | D1 | input | Data input of flip-flop 1, transferred to Q1 on the positive-going clock edge; inputs must stay between GND and VCC. |
| 6 | ~{Q1} | output | Inverted complementary output of flip-flop 1. |
| 7 | Q1 | output | True (non-inverted) output of flip-flop 1, which follows D1 on the next positive-going clock edge. |
| 8 | GND | power_in | Ground reference for all voltages; the datasheet references VIN, VOUT and VCC to GND. |
| 9 | CLOCK | input | Common clock input shared by all four flip-flops; data is latched on the positive-going edge. |
| 10 | Q2 | output | True (non-inverted) output of flip-flop 2, which follows D2 on the next positive-going clock edge. |
| 11 | ~{Q2} | output | Inverted complementary output of flip-flop 2. |
| 12 | D2 | input | Data input of flip-flop 2, transferred to Q2 on the positive-going clock edge; inputs must stay between GND and VCC. |
| 13 | D3 | input | Data input of flip-flop 3, transferred to Q3 on the positive-going clock edge; inputs must stay between GND and VCC. |
| 14 | ~{Q3} | output | Inverted complementary output of flip-flop 3. |
| 15 | Q3 | output | True (non-inverted) output of flip-flop 3, which follows D3 on the next positive-going clock edge. |
| 16 | VCC | power_in | Positive supply pin; the recommended operating supply range is 2.0 V to 6.0 V referenced to GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic ICs |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage | VCC | -0.5 | | 7 | V | Referenced to GND | 3 |
| DC input voltage | Vin | -0.5 | | | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 3 |
| DC output voltage | Vout | -0.5 | | | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 3 |
| DC input current, per pin | Iin | -20 | | 20 | mA | Per pin | 3 |
| DC output current, per pin | Iout | -25 | | 25 | mA | Per pin | 3 |
| DC supply current, VCC and GND pins | ICC | -50 | | 50 | mA | VCC and GND pins | 3 |
| Power dissipation in still air | PD | | | 500 | mW | Still air, SOIC package | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Lead temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds (plastic DIP, SOIC or TSSOP package) | 3 |
| Power dissipation derating | | | -7 | | mW/°C | SOIC package, derate from 65 to 125 °C | 3 |
| DC supply voltage | VCC | 2 | | 6 | V | Referenced to GND | 3 |
| DC input and output voltage | Vin, Vout | 0 | | | V | Referenced to GND; upper limit printed as VCC | 3 |
| Operating temperature, all package types | TA | -55 | | 125 | °C | | 3 |
| Input rise and fall time | tr, tf | 0 | | 1000 | ns | VCC = 2.0 V (Figure 1) | 3 |
| Input rise and fall time | tr, tf | 0 | | 600 | ns | VCC = 3.0 V (Figure 1) | 3 |
| Input rise and fall time | tr, tf | 0 | | 500 | ns | VCC = 4.5 V (Figure 1) | 3 |
| Input rise and fall time | tr, tf | 0 | | 400 | ns | VCC = 6.0 V (Figure 1) | 3 |
| Minimum high-level input voltage | VIH | 1.5 | | | V | VCC = 2.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Minimum high-level input voltage | VIH | 2.1 | | | V | VCC = 3.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Minimum high-level input voltage | VIH | 3.15 | | | V | VCC = 4.5 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Minimum high-level input voltage | VIH | 4.2 | | | V | VCC = 6.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Maximum low-level input voltage | VIL | | | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Maximum low-level input voltage | VIL | | | 0.9 | V | VCC = 3.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Maximum low-level input voltage | VIL | | | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Maximum low-level input voltage | VIL | | | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Minimum high-level output voltage | VOH | 1.9 | | | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Minimum high-level output voltage | VOH | 4.4 | | | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Minimum high-level output voltage | VOH | 5.9 | | | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Minimum high-level output voltage | VOH | 2.2 | | | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; limit at 125 °C | 4 |
| Minimum high-level output voltage | VOH | 3.7 | | | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; limit at 125 °C | 4 |
| Minimum high-level output voltage | VOH | 5.2 | | | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; limit at 125 °C | 4 |
| Maximum low-level output voltage | VOL | | | 0.1 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; −55 to 125 °C | 4 |
| Maximum low-level output voltage | VOL | | | 0.4 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; limit at 125 °C | 4 |
| Maximum input leakage current | Iin | -1 | | 1 | µA | VCC = 6.0 V; Vin = VCC or GND; limit at 125 °C | 4 |
| Maximum quiescent supply current (per package) | ICC | | | 160 | µA | VCC = 6.0 V; Vin = VCC or GND; Iout = 0 µA; limit at 125 °C | 4 |
| Maximum clock frequency (50% duty cycle) | fmax | 4 | | | MHz | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum clock frequency (50% duty cycle) | fmax | 6 | | | MHz | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum clock frequency (50% duty cycle) | fmax | 20 | | | MHz | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum clock frequency (50% duty cycle) | fmax | 24 | | | MHz | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum propagation delay, clock to Q or Q̅ | tPLH, tPHL | | | 225 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum propagation delay, clock to Q or Q̅ | tPLH, tPHL | | | 110 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum propagation delay, clock to Q or Q̅ | tPLH, tPHL | | | 38 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum propagation delay, clock to Q or Q̅ | tPLH, tPHL | | | 33 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum propagation delay, reset to Q or Q̅ | tPHL | | | 190 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum propagation delay, reset to Q or Q̅ | tPHL | | | 110 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum propagation delay, reset to Q or Q̅ | tPHL | | | 34 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum propagation delay, reset to Q or Q̅ | tPHL | | | 30 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum output transition time, any output | tTLH, tTHL | | | 110 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum output transition time, any output | tTLH, tTHL | | | 36 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum output transition time, any output | tTLH, tTHL | | | 22 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum output transition time, any output | tTLH, tTHL | | | 19 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Maximum input capacitance | Cin | | | 10 | pF | | 5 |
| Minimum setup time, data to clock | tsu | 150 | | | ns | VCC = 2.0 V; Figure 3; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Minimum setup time, data to clock | tsu | 85 | | | ns | VCC = 3.0 V; Figure 3; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Minimum setup time, data to clock | tsu | 30 | | | ns | VCC = 4.5 V; Figure 3; input tr = tf = 6 ns; limit at 125 °C | 5 |
| Minimum setup time, data to clock | tsu | 26 | | | ns | VCC = 6.0 V; Figure 3; input tr = tf = 6 ns; limit at 125 °C | 5 |
## CAD (KiCad official)
- Symbol: `MC74HC175ADG`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `mc74hc175adg-etched.step` / `mc74hc175adg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hc175adg.step` / `mc74hc175adg.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hc175a-d.pdf) (10 pp, sha256 `b9d415769bbcaf08`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hc175adg-datasheet.pdf)