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MC74HC165AMNTWG

Public Made by Adom

by adom

onsemi Pre-ordered Products, DHVQFN-16-EP(2.5x3.5). Pinout settled in review by an AI reviewer against the manufacturer's datasheet, KiCad symbol/footprint/3D.

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MC74HC165AMNTWG

onsemi · Pre-ordered Products · DHVQFN-16-EP(2.5x3.5)

MC74HC165AMNTWG from onsemi, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SERIAL SHIFT/~{PARALLEL LOAD} input Data-entry control input: high shifts SA data in on the rising Clock edge, low asynchronously loads the parallel data inputs into the eight stages.
2 CLOCK input Clock input that functions identically to Clock Inhibit and may be used as an active-high clock inhibit, with the shift register static down to DC.
3 E input Parallel data input E, asynchronously loaded into its internal flip-flop when Serial Shift/Parallel Load is low.
4 F input Parallel data input F, asynchronously loaded into its internal flip-flop when Serial Shift/Parallel Load is low.
5 G input Parallel data input G, asynchronously loaded into its internal flip-flop when Serial Shift/Parallel Load is low.
6 H input Parallel data input H, asynchronously loaded into its internal flip-flop when Serial Shift/Parallel Load is low.
7 ~{QH} output Inverted (complementary) output of the eighth stage of the shift register.
8 GND power_in Ground pin (PIN 8 = GND), reference for all voltages.
9 QH output Noninverted output of the eighth stage of the shift register.
10 SA input Serial data input, shifted into the first stage on the rising edge of Clock when Serial Shift/Parallel Load is high.
11 A input Parallel data input A, asynchronously loaded into its internal flip-flop when Serial Shift/Parallel Load is low.
12 B input Parallel data input B, asynchronously loaded into its internal flip-flop when Serial Shift/Parallel Load is low.
13 C input Parallel data input C, asynchronously loaded into its internal flip-flop when Serial Shift/Parallel Load is low.
14 D input Parallel data input D, asynchronously loaded into its internal flip-flop when Serial Shift/Parallel Load is low.
15 CLOCK INHIBIT input Clock input functioning identically to Clock and usable as an active-high clock inhibit, which should go high only while Clock is high to avoid double clocking.
16 VCC power_in Supply pin (PIN 16 = VCC), recommended operating range 2.0 to 6.0 V with an absolute maximum of -0.5 to +7.0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package DHVQFN-16-EP(2.5x3.5)
Category Solders / Accessories / Batteries
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage (Referenced to GND) VCC -0.5 7 V 3
DC Input Voltage (Referenced to GND) Vin -0.5 V 3
DC Output Voltage (Referenced to GND) Vout -0.5 V 3
DC Input Current, per Pin Iin -20 20 mA 3
DC Output Current, per Pin Iout -25 25 mA 3
DC Supply Current, VCC and GND Pins ICC -50 50 mA 3
Storage Temperature Tstg -65 150 °C 3
DC Supply Voltage (Referenced to GND) VCC 2 6 V 3
DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout 0 V 3
Operating Temperature, All Package Types TA -55 125 °C 3
Input Rise and Fall Time tr, tf 0 1000 ns VCC = 2.0 V (Figure 1) 3
Input Rise and Fall Time tr, tf 0 600 ns VCC = 3.0 V (Figure 1) 3
Input Rise and Fall Time tr, tf 0 500 ns VCC = 4.5 V (Figure 1) 3
Input Rise and Fall Time tr, tf 0 400 ns VCC = 6.0 V (Figure 1) 3
Minimum High-Level Input Voltage VIH 1.5 V Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; VCC = 2.0 V 3
Minimum High-Level Input Voltage VIH 2.1 V Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; VCC = 3.0 V 3
Minimum High-Level Input Voltage VIH 3.15 V Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; VCC = 4.5 V 3
Minimum High-Level Input Voltage VIH 4.2 V Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; VCC = 6.0 V 3
Maximum Low-Level Input Voltage VIL 0.5 V Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; VCC = 2.0 V 3
Maximum Low-Level Input Voltage VIL 0.9 V Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; VCC = 3.0 V 3
Maximum Low-Level Input Voltage VIL 1.35 V Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; VCC = 4.5 V 3
Maximum Low-Level Input Voltage VIL 1.8 V Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; VCC = 6.0 V 3
Minimum High-Level Output Voltage VOH 1.9 V Vin = VIH or VIL; /Iout/ <= 20 uA; VCC = 2.0 V 3
Minimum High-Level Output Voltage VOH 4.4 V Vin = VIH or VIL; /Iout/ <= 20 uA; VCC = 4.5 V 3
Minimum High-Level Output Voltage VOH 5.9 V Vin = VIH or VIL; /Iout/ <= 20 uA; VCC = 6.0 V 3
Minimum High-Level Output Voltage VOH 2.2 V Vin = VIH or VIL; /Iout/ <= 2.4 mA; VCC = 3.0 V; 125 °C column 3
Minimum High-Level Output Voltage VOH 3.7 V Vin = VIH or VIL; /Iout/ <= 4.0 mA; VCC = 4.5 V; 125 °C column 3
Minimum High-Level Output Voltage VOH 5.2 V Vin = VIH or VIL; /Iout/ <= 5.2 mA; VCC = 6.0 V; 125 °C column 3
Maximum Low-Level Output Voltage VOL 0.1 V Vin = VIH or VIL; /Iout/ <= 20 uA; VCC = 2.0 V 4
Maximum Low-Level Output Voltage VOL 0.4 V Vin = VIH or VIL; /Iout/ <= 2.4 mA; VCC = 3.0 V; 125 °C column 4
Maximum Input Leakage Current Iin -1 1 uA Vin = VCC or GND; VCC = 6.0 V; 125 °C column 4
Maximum Quiescent Supply Current (per Package) ICC 160 uA Vin = VCC or GND; Iout = 0 uA; VCC = 6.0 V; 125 °C column 4
Maximum Clock Frequency (50% Duty Cycle) fmax 4 MHz CL = 50 pF; Input tr = tf = 6 ns; VCC = 2.0 V; Figures 1 and 8; 125 °C column 4
Maximum Clock Frequency (50% Duty Cycle) fmax 15 MHz CL = 50 pF; Input tr = tf = 6 ns; VCC = 3.0 V; Figures 1 and 8; 125 °C column 4
Maximum Clock Frequency (50% Duty Cycle) fmax 20 MHz CL = 50 pF; Input tr = tf = 6 ns; VCC = 4.5 V; Figures 1 and 8; 125 °C column 4
Maximum Clock Frequency (50% Duty Cycle) fmax 24 MHz CL = 50 pF; Input tr = tf = 6 ns; VCC = 6.0 V; Figures 1 and 8; 125 °C column 4
Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH tPLH, tPHL 225 ns CL = 50 pF; Input tr = tf = 6 ns; VCC = 2.0 V; Figures 1 and 8; 125 °C column 4
Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH tPLH, tPHL 65 ns CL = 50 pF; Input tr = tf = 6 ns; VCC = 3.0 V; Figures 1 and 8; 125 °C column 4
Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH tPLH, tPHL 45 ns CL = 50 pF; Input tr = tf = 6 ns; VCC = 4.5 V; Figures 1 and 8; 125 °C column 4
Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH tPLH, tPHL 38 ns CL = 50 pF; Input tr = tf = 6 ns; VCC = 6.0 V; Figures 1 and 8; 125 °C column 4
Maximum Output Transition Time, Any Output tTLH, tTHL 110 ns CL = 50 pF; Input tr = tf = 6 ns; VCC = 2.0 V; Figures 1 and 8; 125 °C column 4
Maximum Output Transition Time, Any Output tTLH, tTHL 36 ns CL = 50 pF; Input tr = tf = 6 ns; VCC = 3.0 V; Figures 1 and 8; 125 °C column 4
Maximum Output Transition Time, Any Output tTLH, tTHL 22 ns CL = 50 pF; Input tr = tf = 6 ns; VCC = 4.5 V; Figures 1 and 8; 125 °C column 4
Maximum Output Transition Time, Any Output tTLH, tTHL 19 ns CL = 50 pF; Input tr = tf = 6 ns; VCC = 6.0 V; Figures 1 and 8; 125 °C column 4
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load tsu 110 ns Input tr = tf = 6 ns; VCC = 2.0 V; Figure 4; 125 °C column 5
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load tsu 55 ns Input tr = tf = 6 ns; VCC = 3.0 V; Figure 4; 125 °C column 5
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load tsu 22 ns Input tr = tf = 6 ns; VCC = 4.5 V; Figure 4; 125 °C column 5
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load tsu 19 ns Input tr = tf = 6 ns; VCC = 6.0 V; Figure 4; 125 °C column 5
Minimum Setup Time, Input SA to Clock (or Clock Inhibit) tsu 110 ns Input tr = tf = 6 ns; VCC = 2.0 V; Figure 5; 125 °C column 5
Minimum Setup Time, Input SA to Clock (or Clock Inhibit) tsu 55 ns Input tr = tf = 6 ns; VCC = 3.0 V; Figure 5; 125 °C column 5
Minimum Setup Time, Input SA to Clock (or Clock Inhibit) tsu 22 ns Input tr = tf = 6 ns; VCC = 4.5 V; Figure 5; 125 °C column 5
Minimum Setup Time, Input SA to Clock (or Clock Inhibit) tsu 19 ns Input tr = tf = 6 ns; VCC = 6.0 V; Figure 5; 125 °C column 5
Minimum Pulse Width, Clock (or Clock Inhibit) tw 100 ns Input tr = tf = 6 ns; VCC = 2.0 V; Figure 1; 125 °C column 5
Minimum Pulse Width, Clock (or Clock Inhibit) tw 36 ns Input tr = tf = 6 ns; VCC = 3.0 V; Figure 1; 125 °C column 5
Minimum Pulse Width, Clock (or Clock Inhibit) tw 22 ns Input tr = tf = 6 ns; VCC = 4.5 V; Figure 1; 125 °C column 5
Minimum Pulse Width, Clock (or Clock Inhibit) tw 19 ns Input tr = tf = 6 ns; VCC = 6.0 V; Figure 1; 125 °C column 5

CAD (KiCad official)

  • Symbol: MC74HC165AMNTWG
  • Footprint: Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm
  • 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: mc74hc165amntwg-etched.step / mc74hc165amntwg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hc165amntwg.step / mc74hc165amntwg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (12 pp, sha256 17a2e32beec9a056, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF