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MC74HC165ADTR2G

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onsemi Shift Registers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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MC74HC165ADTR2G

onsemi · Shift Registers · TSSOP-16

MC74HC165ADTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SH/LD input Serial Shift/Parallel Load control input; low = asynchronous parallel load of pins A-H into all eight stages; high = serial shift into register on rising edge of Clock or Clock Inhibit.
2 CLK input Clock input; shift register advances on rising edge when Serial Shift/Parallel Load is high; can function as active-high clock inhibit (inhibit should go high only while the other clock input is high to avoid double clocking); minimum pulse width 15 ns at VCC = 4.5 V.
3 E input Parallel data input E; asynchronously loaded into the fifth internal flip-flop stage when Serial Shift/Parallel Load is low; VIH min 3.15 V, VIL max 1.35 V at VCC = 4.5 V.
4 F input Parallel data input F; asynchronously loaded into the sixth internal flip-flop stage when Serial Shift/Parallel Load is low; VIH min 3.15 V, VIL max 1.35 V at VCC = 4.5 V.
5 G input Parallel data input G; asynchronously loaded into the seventh internal flip-flop stage when Serial Shift/Parallel Load is low; VIH min 3.15 V, VIL max 1.35 V at VCC = 4.5 V.
6 H input Parallel data input H; asynchronously loaded into the eighth internal flip-flop stage when Serial Shift/Parallel Load is low; VIH min 3.15 V, VIL max 1.35 V at VCC = 4.5 V.
7 /QH output Inverted complementary serial output of the eighth shift register stage; VOH min 3.98 V, VOL max 0.26 V at VCC = 4.5 V,
8 GND power_in Ground reference; DC supply current ICC max ±50 mA; all voltages referenced to this pin.
9 QH output Non-inverted serial output of the eighth shift register stage; VOH min 3.98 V, VOL max 0.26 V at VCC = 4.5 V,
10 SA input Serial data input; data present on this pin is shifted into the first stage of the shift register on the rising edge of Clock when Serial Shift/Parallel Load is high; Iin max ±0.1 µA at VCC = 6.0 V.
11 A input Parallel data input A; asynchronously loaded into the first internal flip-flop stage when Serial Shift/Parallel Load is low; VIH min 3.15 V, VIL max 1.35 V at VCC = 4.5 V.
12 B input Parallel data input B; asynchronously loaded into the second internal flip-flop stage when Serial Shift/Parallel Load is low; VIH min 3.15 V, VIL max 1.35 V at VCC = 4.5 V.
13 C input Parallel data input C; asynchronously loaded into the third internal flip-flop stage when Serial Shift/Parallel Load is low; VIH min 3.15 V, VIL max 1.35 V at VCC = 4.5 V.
14 D input Parallel data input D; asynchronously loaded into the fourth internal flip-flop stage when Serial Shift/Parallel Load is low; VIH min 3.15 V, VIL max 1.35 V at VCC = 4.5 V.
15 CLK_INH input Clock Inhibit input; functions identically to the Clock pin and can be used as an active-high clock inhibit; to avoid double clocking, this input should go high only while the Clock input is high; minimum pulse width 15 ns at VCC = 4.5 V.
16 VCC power_in Positive DC supply voltage; operating range 2.0 V to 6.0 V; maximum rated voltage 7.0 V; quiescent ICC max 4 µA at 25 °C, VCC = 6.0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: MC74HC165ADTR2G
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: mc74hc165adtr2g-etched.step / mc74hc165adtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hc165adtr2g.step / mc74hc165adtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (12 pp, sha256 40ad15f35b7ec5a5, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF