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MC74HC164ADTR2G

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onsemi Shift Registers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74HC164ADTR2G

onsemi · Shift Registers · TSSOP-14

MC74HC164ADTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Serial data input; a high level is entered into the first stage only when both A1 and A2 are high, so one input can serve as a data enable, and an unused serial input must be tied to VCC.
2 A2 input Serial data input; a high level is entered into the first stage only when both A1 and A2 are high, so one input can serve as a data enable, and an unused serial input must be tied to VCC.
3 QA output Parallel shift register output, presented in true (non-inverted) form; unused outputs must be left open.
4 QB output Parallel shift register output, presented in true (non-inverted) form; unused outputs must be left open.
5 QC output Parallel shift register output, presented in true (non-inverted) form; unused outputs must be left open.
6 QD output Parallel shift register output, presented in true (non-inverted) form; unused outputs must be left open.
7 GND power_in Ground reference pin for all voltages (VCC range 2.0 V to 6.0 V referenced to GND).
8 CLOCK input Shift register clock; data shifts to the next stage on each positive-going transition, and the register is static so clock rates down to DC are allowed.
9 RESET input Active-low asynchronous reset; a low level resets all flip-flops and forces QA-QH low, overriding the clock and serial data inputs.
10 QE output Parallel shift register output, presented in true (non-inverted) form; unused outputs must be left open.
11 QF output Parallel shift register output, presented in true (non-inverted) form; unused outputs must be left open.
12 QG output Parallel shift register output, presented in true (non-inverted) form; unused outputs must be left open.
13 QH output Parallel shift register output, presented in true (non-inverted) form; unused outputs must be left open.
14 VCC power_in Positive supply pin; the recommended operating range is 2.0 V to 6.0 V and the absolute maximum is -0.5 V to +7.0 V referenced to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage (Referenced to GND) VCC 2 6 V 3
DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout 0 V Maximum printed as VCC 3
Operating Temperature, All Package Types TA -55 125 C 3
Input Rise and Fall Time tr, tf 0 1000 ns VCC = 2.0 V (Figure 1) 3
Input Rise and Fall Time tr, tf 0 500 ns VCC = 4.5 V (Figure 1) 3
Input Rise and Fall Time tr, tf 0 400 ns VCC = 6.0 V (Figure 1) 3
DC Supply Voltage (Referenced to GND) VCC -0.5 7 V 3
DC Input Voltage (Referenced to GND) Vin -0.5 V Maximum printed as VCC + 0.5 3
DC Output Voltage (Referenced to GND) Vout -0.5 V Maximum printed as VCC + 0.5 3
DC Input Current, per Pin Iin -20 20 mA 3
DC Output Current, per Pin Iout -25 25 mA 3
DC Supply Current, VCC and GND Pins ICC -50 50 mA 3
Power Dissipation in Still Air, TSSOP Package PD 450 mW Still air, TSSOP package 3
Storage Temperature Tstg -65 150 C 3
Lead Temperature TL 260 C 1 mm from case for 10 seconds (Plastic DIP, SOIC or TSSOP) 3
Minimum High-Level Input Voltage VIH 1.5 V VCC = 2.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA 3
Minimum High-Level Input Voltage VIH 2.1 V VCC = 3.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA 3
Minimum High-Level Input Voltage VIH 3.15 V VCC = 4.5 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA 3
Minimum High-Level Input Voltage VIH 4.2 V VCC = 6.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA 3
Maximum Low-Level Input Voltage VIL 0.5 V VCC = 2.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA 3
Maximum Low-Level Input Voltage VIL 0.9 V VCC = 3.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA 3
Maximum Low-Level Input Voltage VIL 1.35 V VCC = 4.5 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA 3
Maximum Low-Level Input Voltage VIL 1.8 V VCC = 6.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA 3
Minimum High-Level Output Voltage VOH 1.9 V VCC = 2.0 V; Vin = VIH or VIL; /Iout/ <= 20 uA 3
Minimum High-Level Output Voltage VOH 4.4 V VCC = 4.5 V; Vin = VIH or VIL; /Iout/ <= 20 uA 3
Minimum High-Level Output Voltage VOH 5.9 V VCC = 6.0 V; Vin = VIH or VIL; /Iout/ <= 20 uA 3
Maximum Low-Level Output Voltage VOL 0.1 V VCC = 2.0 V; Vin = VIH or VIL; /Iout/ <= 20 uA 4
Minimum High-Level Output Voltage VOH 2.2 V VCC = 3.0 V; Vin = VIH or VIL; /Iout/ <= 2.4 mA; TA = 125 C (worst case of -55 to 125 C) 3
Minimum High-Level Output Voltage VOH 3.7 V VCC = 4.5 V; Vin = VIH or VIL; /Iout/ <= 4.0 mA; TA = 125 C (worst case of -55 to 125 C) 3
Minimum High-Level Output Voltage VOH 5.2 V VCC = 6.0 V; Vin = VIH or VIL; /Iout/ <= 5.2 mA; TA = 125 C (worst case of -55 to 125 C) 3
Maximum Low-Level Output Voltage VOL 0.4 V VCC = 3.0 V; Vin = VIH or VIL; /Iout/ <= 2.4 mA; TA = 125 C (worst case of -55 to 125 C) 4
Maximum Input Leakage Current Iin -1 1 uA VCC = 6.0 V; Vin = VCC or GND; TA = 125 C 4
Maximum Quiescent Supply Current (per Package) ICC 160 uA VCC = 6.0 V; Vin = VCC or GND; Iout = 0 A; TA = 125 C 4
Maximum Clock Frequency (50% Duty Cycle) fmax 10 MHz VCC = 2.0 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Clock Frequency (50% Duty Cycle) fmax 20 MHz VCC = 3.0 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Clock Frequency (50% Duty Cycle) fmax 30 MHz VCC = 4.5 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Clock Frequency (50% Duty Cycle) fmax 40 MHz VCC = 6.0 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Propagation Delay, Clock to Q tPLH, tPHL 250 ns VCC = 2.0 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Propagation Delay, Clock to Q tPLH, tPHL 200 ns VCC = 3.0 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Propagation Delay, Clock to Q tPLH, tPHL 48 ns VCC = 4.5 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Propagation Delay, Clock to Q tPLH, tPHL 42 ns VCC = 6.0 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Propagation Delay, Reset to Q tPHL 260 ns VCC = 2.0 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Propagation Delay, Reset to Q tPHL 200 ns VCC = 3.0 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Propagation Delay, Reset to Q tPHL 53 ns VCC = 4.5 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Maximum Propagation Delay, Reset to Q tPHL 45 ns VCC = 6.0 V; CL = 50 pF; tr = tf = 6 ns; TA = 125 C 4
Minimum Setup Time, A1 or A2 to Clock tsu 40 ns VCC = 2.0 V; TA = 125 C (Figure 3) 5
Minimum Setup Time, A1 or A2 to Clock tsu 25 ns VCC = 3.0 V; TA = 125 C (Figure 3) 5
Minimum Setup Time, A1 or A2 to Clock tsu 9 ns VCC = 4.5 V; TA = 125 C (Figure 3) 5
Minimum Setup Time, A1 or A2 to Clock tsu 6 ns VCC = 6.0 V; TA = 125 C (Figure 3) 5
Minimum Pulse Width, Clock tw 75 ns VCC = 2.0 V; TA = 125 C (Figure 1) 5
Minimum Pulse Width, Clock tw 45 ns VCC = 3.0 V; TA = 125 C (Figure 1) 5
Minimum Pulse Width, Clock tw 20 ns VCC = 4.5 V; TA = 125 C (Figure 1) 5
Minimum Pulse Width, Clock tw 15 ns VCC = 6.0 V; TA = 125 C (Figure 1) 5
Maximum Input Capacitance Cin 10 pF 4

CAD (KiCad official)

  • Symbol: MC74HC164ADTR2G
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: mc74hc164adtr2g-etched.step / mc74hc164adtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hc164adtr2g.step / mc74hc164adtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (11 pp, sha256 a1c89f9dfc62e83e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF