component
MC74HC164ADR2G
Public Made by Adomby adom
onsemi Shift Registers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MC74HC164ADR2G
onsemi · Shift Registers · SOIC-14
MC74HC164ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Serial data input; A1 and A2 must both be high to enter a high into the first stage, so one input can act as a data enable, and an unused serial input must be tied to VCC. |
| 2 | A2 | input | Serial data input; A1 and A2 must both be high to enter a high into the first stage, so one input can act as a data enable, and an unused serial input must be tied to VCC. |
| 3 | QA | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 4 | QB | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 5 | QC | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 6 | QD | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 7 | GND | power_in | Ground reference; all voltages are referenced to this pin. |
| 8 | CLOCK | input | Shift register clock; data shifts one stage on each positive-going transition, and the register is static so clock rates down to DC are allowed. |
| 9 | RESET | input | Active-low asynchronous reset; a low voltage resets all internal flip-flops and forces QA to QH low, overriding the clock and serial data inputs. |
| 10 | QE | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 11 | QF | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 12 | QG | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 13 | QH | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 14 | VCC | power_in | Positive supply; the device operates from 2.0 V to 6.0 V DC referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | 3 | ||
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | Max = VCC | 3 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | °C | 3 | ||
| Input Rise and Fall Time (Figure 1) | tr, tf | 0 | 1000 | ns | VCC = 2.0 V | 3 | |
| Input Rise and Fall Time (Figure 1) | tr, tf | 0 | 500 | ns | VCC = 4.5 V | 3 | |
| Input Rise and Fall Time (Figure 1) | tr, tf | 0 | 400 | ns | VCC = 6.0 V | 3 | |
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | 3 | ||
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | Max = VCC + 0.5 V | 3 | ||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | Max = VCC + 0.5 V | 3 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | 3 | ||
| DC Output Current, per Pin | Iout | -25 | 25 | mA | 3 | ||
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | 3 | ||
| Power Dissipation in Still Air, SOIC Package | PD | 500 | mW | Still air, SOIC package | 3 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 3 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds (SOIC package) | 3 | ||
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Input Voltage | VIH | 2.1 | V | VCC = 3.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | VCC = 3.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.9 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 2.2 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; 125°C limit | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; 125°C limit | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.2 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; 125°C limit | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.26 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.33 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA | 4 | ||
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | VCC = 6.0 V; Vin = VCC or GND; 125°C limit | 4 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | µA | VCC = 6.0 V; Vin = VCC or GND; Iout = 0 A; 125°C limit | 4 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 4 | |||
| Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) | fmax | 10 | MHz | VCC = 2.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) | fmax | 20 | MHz | VCC = 3.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) | fmax | 30 | MHz | VCC = 4.5 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) | fmax | 40 | MHz | VCC = 6.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Propagation Delay, Clock to Q (Figures 1 and 4) | tPLH, tPHL | 250 | ns | VCC = 2.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Propagation Delay, Clock to Q (Figures 1 and 4) | tPLH, tPHL | 200 | ns | VCC = 3.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Propagation Delay, Clock to Q (Figures 1 and 4) | tPLH, tPHL | 48 | ns | VCC = 4.5 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Propagation Delay, Clock to Q (Figures 1 and 4) | tPLH, tPHL | 42 | ns | VCC = 6.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Propagation Delay, Reset to Q (Figures 2 and 4) | tPHL | 260 | ns | VCC = 2.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Propagation Delay, Reset to Q (Figures 2 and 4) | tPHL | 200 | ns | VCC = 3.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Propagation Delay, Reset to Q (Figures 2 and 4) | tPHL | 53 | ns | VCC = 4.5 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Propagation Delay, Reset to Q (Figures 2 and 4) | tPHL | 45 | ns | VCC = 6.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Output Transition Time, Any Output (Figures 1 and 4) | tTLH, tTHL | 110 | ns | VCC = 2.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Output Transition Time, Any Output (Figures 1 and 4) | tTLH, tTHL | 36 | ns | VCC = 3.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Output Transition Time, Any Output (Figures 1 and 4) | tTLH, tTHL | 22 | ns | VCC = 4.5 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Maximum Output Transition Time, Any Output (Figures 1 and 4) | tTLH, tTHL | 19 | ns | VCC = 6.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 | ||
| Minimum Setup Time, A1 or A2 to Clock (Figure 3) | tsu | 40 | ns | VCC = 2.0 V; 125°C limit | 5 | ||
| Minimum Setup Time, A1 or A2 to Clock (Figure 3) | tsu | 25 | ns | VCC = 3.0 V; 125°C limit | 5 | ||
| Minimum Setup Time, A1 or A2 to Clock (Figure 3) | tsu | 9 | ns | VCC = 4.5 V; 125°C limit | 5 | ||
| Minimum Setup Time, A1 or A2 to Clock (Figure 3) | tsu | 6 | ns | VCC = 6.0 V; 125°C limit | 5 | ||
| Minimum Hold Time, Clock to A1 or A2 (Figure 3) | th | 3 | ns | VCC = 2.0, 3.0, 4.5 and 6.0 V (same value at each VCC) | 5 | ||
| Minimum Recovery Time, Reset Inactive to Clock (Figure 2) | trec | 3 | ns | VCC = 2.0, 3.0, 4.5 and 6.0 V (same value at each VCC) | 5 |
CAD (KiCad official)
- Symbol:
MC74HC164ADR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74hc164adr2g-etched.step/mc74hc164adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc164adr2g.step/mc74hc164adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (11 pp, sha256
a1c89f9dfc62e83e, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HC164ADR2G
**onsemi** · Shift Registers · SOIC-14
MC74HC164ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Serial data input; A1 and A2 must both be high to enter a high into the first stage, so one input can act as a data enable, and an unused serial input must be tied to VCC. |
| 2 | A2 | input | Serial data input; A1 and A2 must both be high to enter a high into the first stage, so one input can act as a data enable, and an unused serial input must be tied to VCC. |
| 3 | QA | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 4 | QB | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 5 | QC | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 6 | QD | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 7 | GND | power_in | Ground reference; all voltages are referenced to this pin. |
| 8 | CLOCK | input | Shift register clock; data shifts one stage on each positive-going transition, and the register is static so clock rates down to DC are allowed. |
| 9 | RESET | input | Active-low asynchronous reset; a low voltage resets all internal flip-flops and forces QA to QH low, overriding the clock and serial data inputs. |
| 10 | QE | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 11 | QF | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 12 | QG | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 13 | QH | output | Parallel shift register output, presented in true (non-inverted) form; set low by an active-low Reset. |
| 14 | VCC | power_in | Positive supply; the device operates from 2.0 V to 6.0 V DC referenced to GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 2 | | 6 | V | | 3 |
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | | | V | Max = VCC | 3 |
| Operating Temperature, All Package Types | TA | -55 | | 125 | °C | | 3 |
| Input Rise and Fall Time (Figure 1) | tr, tf | 0 | | 1000 | ns | VCC = 2.0 V | 3 |
| Input Rise and Fall Time (Figure 1) | tr, tf | 0 | | 500 | ns | VCC = 4.5 V | 3 |
| Input Rise and Fall Time (Figure 1) | tr, tf | 0 | | 400 | ns | VCC = 6.0 V | 3 |
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | | 7 | V | | 3 |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | | | V | Max = VCC + 0.5 V | 3 |
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | | | V | Max = VCC + 0.5 V | 3 |
| DC Input Current, per Pin | Iin | -20 | | 20 | mA | | 3 |
| DC Output Current, per Pin | Iout | -25 | | 25 | mA | | 3 |
| DC Supply Current, VCC and GND Pins | ICC | -50 | | 50 | mA | | 3 |
| Power Dissipation in Still Air, SOIC Package | PD | | | 500 | mW | Still air, SOIC package | 3 |
| Storage Temperature | Tstg | -65 | | 150 | °C | | 3 |
| Lead Temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds (SOIC package) | 3 |
| Minimum High-Level Input Voltage | VIH | 1.5 | | | V | VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 |
| Minimum High-Level Input Voltage | VIH | 2.1 | | | V | VCC = 3.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 |
| Minimum High-Level Input Voltage | VIH | 3.15 | | | V | VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 |
| Minimum High-Level Input Voltage | VIH | 4.2 | | | V | VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 |
| Maximum Low-Level Input Voltage | VIL | | | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 |
| Maximum Low-Level Input Voltage | VIL | | | 0.9 | V | VCC = 3.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 |
| Maximum Low-Level Input Voltage | VIL | | | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 |
| Maximum Low-Level Input Voltage | VIL | | | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 3 |
| Minimum High-Level Output Voltage | VOH | 1.9 | | | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 3 |
| Minimum High-Level Output Voltage | VOH | 4.4 | | | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 3 |
| Minimum High-Level Output Voltage | VOH | 5.9 | | | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 3 |
| Minimum High-Level Output Voltage | VOH | 2.2 | | | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; 125°C limit | 3 |
| Minimum High-Level Output Voltage | VOH | 3.7 | | | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; 125°C limit | 3 |
| Minimum High-Level Output Voltage | VOH | 5.2 | | | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; 125°C limit | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.1 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 |
| Maximum Low-Level Output Voltage | VOL | | | 0.26 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA | 4 |
| Maximum Low-Level Output Voltage | VOL | | | 0.33 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA | 4 |
| Maximum Low-Level Output Voltage | VOL | | | 0.4 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA | 4 |
| Maximum Input Leakage Current | Iin | -1 | | 1 | µA | VCC = 6.0 V; Vin = VCC or GND; 125°C limit | 4 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 160 | µA | VCC = 6.0 V; Vin = VCC or GND; Iout = 0 A; 125°C limit | 4 |
| Maximum Input Capacitance | Cin | | | 10 | pF | | 4 |
| Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) | fmax | 10 | | | MHz | VCC = 2.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) | fmax | 20 | | | MHz | VCC = 3.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) | fmax | 30 | | | MHz | VCC = 4.5 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) | fmax | 40 | | | MHz | VCC = 6.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Propagation Delay, Clock to Q (Figures 1 and 4) | tPLH, tPHL | | | 250 | ns | VCC = 2.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Propagation Delay, Clock to Q (Figures 1 and 4) | tPLH, tPHL | | | 200 | ns | VCC = 3.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Propagation Delay, Clock to Q (Figures 1 and 4) | tPLH, tPHL | | | 48 | ns | VCC = 4.5 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Propagation Delay, Clock to Q (Figures 1 and 4) | tPLH, tPHL | | | 42 | ns | VCC = 6.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Propagation Delay, Reset to Q (Figures 2 and 4) | tPHL | | | 260 | ns | VCC = 2.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Propagation Delay, Reset to Q (Figures 2 and 4) | tPHL | | | 200 | ns | VCC = 3.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Propagation Delay, Reset to Q (Figures 2 and 4) | tPHL | | | 53 | ns | VCC = 4.5 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Propagation Delay, Reset to Q (Figures 2 and 4) | tPHL | | | 45 | ns | VCC = 6.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Output Transition Time, Any Output (Figures 1 and 4) | tTLH, tTHL | | | 110 | ns | VCC = 2.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Output Transition Time, Any Output (Figures 1 and 4) | tTLH, tTHL | | | 36 | ns | VCC = 3.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Output Transition Time, Any Output (Figures 1 and 4) | tTLH, tTHL | | | 22 | ns | VCC = 4.5 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Maximum Output Transition Time, Any Output (Figures 1 and 4) | tTLH, tTHL | | | 19 | ns | VCC = 6.0 V; CL = 50 pF, Input tr = tf = 6 ns; 125°C limit | 4 |
| Minimum Setup Time, A1 or A2 to Clock (Figure 3) | tsu | 40 | | | ns | VCC = 2.0 V; 125°C limit | 5 |
| Minimum Setup Time, A1 or A2 to Clock (Figure 3) | tsu | 25 | | | ns | VCC = 3.0 V; 125°C limit | 5 |
| Minimum Setup Time, A1 or A2 to Clock (Figure 3) | tsu | 9 | | | ns | VCC = 4.5 V; 125°C limit | 5 |
| Minimum Setup Time, A1 or A2 to Clock (Figure 3) | tsu | 6 | | | ns | VCC = 6.0 V; 125°C limit | 5 |
| Minimum Hold Time, Clock to A1 or A2 (Figure 3) | th | 3 | | | ns | VCC = 2.0, 3.0, 4.5 and 6.0 V (same value at each VCC) | 5 |
| Minimum Recovery Time, Reset Inactive to Clock (Figure 2) | trec | 3 | | | ns | VCC = 2.0, 3.0, 4.5 and 6.0 V (same value at each VCC) | 5 |
## CAD (KiCad official)
- Symbol: `MC74HC164ADR2G`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `mc74hc164adr2g-etched.step` / `mc74hc164adr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hc164adr2g.step` / `mc74hc164adr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586192617990602752) (11 pp, sha256 `a1c89f9dfc62e83e`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hc164adr2g-datasheet.pdf)