component
MC74HC157ADR2G
Public Made by Adomby adom
onsemi Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HC157ADR2G
onsemi · Signal Switches, Multiplexers, Decoders · SOIC-16
MC74HC157ADR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SELECT | input | Nibble select input; a low level selects the A0-A3 inputs and a high level selects the B0-B3 inputs for transfer to the Y outputs. |
| 2 | A0 | input | Nibble A data input 0, transferred noninverted to Y0 when Select is low and Output Enable is low; unused inputs must be tied to GND or VCC. |
| 3 | B0 | input | Nibble B data input 0, transferred noninverted to Y0 when Select is high and Output Enable is low; unused inputs must be tied to GND or VCC. |
| 4 | Y0 | output | Data output 0, presenting the selected nibble bit in noninverted form when Output Enable is low and forced to a low level when Output Enable is high. |
| 5 | A1 | input | Nibble A data input 1, transferred noninverted to Y1 when Select is low and Output Enable is low; unused inputs must be tied to GND or VCC. |
| 6 | B1 | input | Nibble B data input 1, transferred noninverted to Y1 when Select is high and Output Enable is low; unused inputs must be tied to GND or VCC. |
| 7 | Y1 | output | Data output 1, presenting the selected nibble bit in noninverted form when Output Enable is low and forced to a low level when Output Enable is high. |
| 8 | GND | power_in | Ground reference pin; all DC input and output voltages are referenced to GND. |
| 9 | Y2 | output | Data output 2, presenting the selected nibble bit in noninverted form when Output Enable is low and forced to a low level when Output Enable is high. |
| 10 | B2 | input | Nibble B data input 2, transferred noninverted to Y2 when Select is high and Output Enable is low; unused inputs must be tied to GND or VCC. |
| 11 | A2 | input | Nibble A data input 2, transferred noninverted to Y2 when Select is low and Output Enable is low; unused inputs must be tied to GND or VCC. |
| 12 | Y3 | output | Data output 3, presenting the selected nibble bit in noninverted form when Output Enable is low and forced to a low level when Output Enable is high. |
| 13 | B3 | input | Nibble B data input 3, transferred noninverted to Y3 when Select is high and Output Enable is low; unused inputs must be tied to GND or VCC. |
| 14 | A3 | input | Nibble A data input 3, transferred noninverted to Y3 when Select is low and Output Enable is low; unused inputs must be tied to GND or VCC. |
| 15 | OUTPUT ENABLE | input | Output Enable input; a low level passes the selected data to the outputs and a high level forces all Y outputs to a low level. |
| 16 | VCC | power_in | Positive supply pin; the recommended DC supply range is 2.0 V to 6.0 V referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | Referenced to GND; printed maximum is VCC + 0.5 | 2 | ||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | Referenced to GND; printed maximum is VCC + 0.5 | 2 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | 2 | ||
| DC Output Current, per Pin | Iout | -25 | 25 | mA | 2 | ||
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | 2 | ||
| Power Dissipation in Still Air, SOIC Package | PD | 500 | mW | Still air, SOIC package | 2 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 2 | ||
| Lead Temperature (SOIC or TSSOP Package) | TL | 260 | °C | 1 mm from case for 10 seconds | 2 | ||
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | Referenced to GND | 2 | |
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | Printed maximum is VCC | 2 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | °C | 2 | ||
| Input Rise and Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V (Figure 1) | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V (Figure 1) | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V (Figure 1) | 2 | |
| Minimum High-Level Input Voltage | VIH | 1.5 | V | Vout = VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V | 3 | ||
| Minimum High-Level Input Voltage | VIH | 2.1 | V | Vout = VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 3.0 V | 3 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | Vout = VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 4.5 V | 3 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | Vout = VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 6.0 V | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | Vout = 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | Vout = 0.1 V; /Iout/ ≤ 20 µA; VCC = 3.0 V | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | Vout = 0.1 V; /Iout/ ≤ 20 µA; VCC = 4.5 V | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | Vout = 0.1 V; /Iout/ ≤ 20 µA; VCC = 6.0 V | 3 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | V | Vin = VIH; /Iout/ ≤ 20 µA; VCC = 2.0 V | 3 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | Vin = VIH; /Iout/ ≤ 20 µA; VCC = 4.5 V | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.9 | V | Vin = VIH; /Iout/ ≤ 20 µA; VCC = 6.0 V | 3 | ||
| Minimum High-Level Output Voltage | VOH | 2.2 | V | Vin = VIH; /Iout/ ≤ 2.4 mA; VCC = 3.0 V | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | Vin = VIH; /Iout/ ≤ 6.0 mA; VCC = 4.5 V | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.2 | V | Vin = VIH; /Iout/ ≤ 7.8 mA; VCC = 6.0 V | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | Vin = VIL; /Iout/ ≤ 20 µA; VCC = 2.0 V | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | Vin = VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V | 3 | ||
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | Vin = VCC or GND; VCC = 6.0 V | 3 | |
| Maximum Three-State Leakage Current | IOZ | -10 | 10 | µA | Output in high-impedance state; Vin = VIL or VIH; Vout = VCC or GND; VCC = 6.0 V | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | µA | Vin = VCC or GND; Iout = 0 µA; VCC = 6.0 V | 3 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 160 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 2.0 V (Figures 1 and 4) | 3 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 115 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 3.0 V (Figures 1 and 4) | 3 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 32 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 4.5 V (Figures 1 and 4) | 3 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 27 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 6.0 V (Figures 1 and 4) | 3 | ||
| Maximum Propagation Delay, Select to Output Y | tPLH, tPHL | 165 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 2.0 V (Figures 2 and 4) | 3 | ||
| Maximum Propagation Delay, Select to Output Y | tPLH, tPHL | 115 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 3.0 V (Figures 2 and 4) | 3 | ||
| Maximum Propagation Delay, Select to Output Y | tPLH, tPHL | 33 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 4.5 V (Figures 2 and 4) | 3 | ||
| Maximum Propagation Delay, Select to Output Y | tPLH, tPHL | 28 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 6.0 V (Figures 2 and 4) | 3 | ||
| Maximum Propagation Delay, Output Enable to Output Y | tPLH, tPHL | 150 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 2.0 V (Figures 3 and 4) | 3 | ||
| Maximum Propagation Delay, Output Enable to Output Y | tPLH, tPHL | 110 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 3.0 V (Figures 3 and 4) | 3 | ||
| Maximum Propagation Delay, Output Enable to Output Y | tPLH, tPHL | 30 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 4.5 V (Figures 3 and 4) | 3 | ||
| Maximum Propagation Delay, Output Enable to Output Y | tPLH, tPHL | 26 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 6.0 V (Figures 3 and 4) | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 110 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 2.0 V (Figures 1 and 4) | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 36 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 3.0 V (Figures 1 and 4) | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 22 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 4.5 V (Figures 1 and 4) | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 19 | ns | CL = 50 pF; Input tr = tf = 6.0 ns; VCC = 6.0 V (Figures 1 and 4) | 3 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 3 |
CAD (KiCad official)
- Symbol:
MC74HC157ADR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hc157adr2g-etched.step/mc74hc157adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc157adr2g.step/mc74hc157adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (8 pp, sha256
dbf69de9b21f2b21, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).