component
MC74HC14ADG
Public Made by Adomby adom
onsemi Inverters, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MC74HC14ADG
onsemi · Inverters · SOIC-14
MC74HC14ADG from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Schmitt-trigger inverter 1 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 2 | Y1 | output | Inverter 1 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 3 | A2 | input | Schmitt-trigger inverter 2 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 4 | Y2 | output | Inverter 2 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 5 | A3 | input | Schmitt-trigger inverter 3 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 6 | Y3 | output | Inverter 3 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 7 | GND | power_in | Ground pin (0 V reference for supply and all logic levels). |
| 8 | Y4 | output | Inverter 4 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 9 | A4 | input | Schmitt-trigger inverter 4 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 10 | Y5 | output | Inverter 5 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 11 | A5 | input | Schmitt-trigger inverter 5 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 12 | Y6 | output | Inverter 6 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 13 | A6 | input | Schmitt-trigger inverter 6 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 14 | VCC | power_in | Positive supply pin, operating range 2.0 to 6.0 V (absolute maximum 6.5 V) for MC74HC14A. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 6.5 | V | 2 | ||
| DC Input Voltage | VIN | -0.5 | V | max is VCC + 0.5 | 2 | ||
| DC Output Voltage | VOUT | -0.5 | V | max is VCC + 0.5 | 2 | ||
| DC Input Current, per Pin | IIN | -20 | 20 | mA | 2 | ||
| DC Output Current, per Pin | IOUT | -25 | 25 | mA | 2 | ||
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | 2 | ||
| Input Clamp Current | IIK | -20 | 20 | mA | VIN < 0 or VIN > VCC | 2 | |
| Output Clamp Current | IOK | -20 | 20 | mA | VOUT < 0 or VOUT > VCC | 2 | |
| Storage Temperature | TSTG | -65 | 150 | °C | 2 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 2 | ||
| Junction Temperature Under Bias | TJ | -150 | 150 | °C | 2 | ||
| ESD Withstand Voltage, HBM | VESD | 4000 | V | Human Body Model | 2 | ||
| ESD Withstand Voltage, CDM | VESD | 1000 | V | Charged Device Model | 2 | ||
| Thermal Resistance | θJA | 116 | °C/W | SOIC-14 NB, FR4 board per JESD51-7 | 2 | ||
| Power Dissipation in Still Air | PD | 1077 | mW | SOIC-14 NB, at 25 °C | 2 | ||
| DC Supply Voltage (MC74HC) | VCC | 2 | 6 | V | Referenced to GND | 2 | |
| DC Input/Output Voltage (MC74HC) | VIN, VOUT | 0 | V | max is VCC; referenced to GND | 2 | ||
| Operating Free-Air Temperature | TA | -55 | 125 | °C | MC74HC | 2 | |
| Maximum Positive-Going Input Threshold Voltage | VT+ max | 3.15 | V | VCC = 4.5 V, Vout = 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 | ||
| Minimum Positive-Going Input Threshold Voltage | VT+ min | 2.3 | V | VCC = 4.5 V, Vout = 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 | ||
| Minimum Positive-Going Input Threshold Voltage | VT+ min | 2.25 | V | VCC = 4.5 V, Vout = 0.1V, /Iout/ ≤ 20µA, ≤125 °C | 3 | ||
| Maximum Negative-Going Input Threshold Voltage | VT− max | 2 | V | VCC = 4.5 V, Vout = VCC − 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 | ||
| Maximum Negative-Going Input Threshold Voltage | VT− max | 2.05 | V | VCC = 4.5 V, Vout = VCC − 0.1V, /Iout/ ≤ 20µA, ≤125 °C | 3 | ||
| Minimum Negative-Going Input Threshold Voltage | VT− min | 0.9 | V | VCC = 4.5 V, Vout = VCC − 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 | ||
| Maximum Hysteresis Voltage | VHmax | 2.25 | V | VCC = 4.5 V, Vout = 0.1V or VCC − 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 | ||
| Minimum Hysteresis Voltage | VHmin | 0.4 | V | VCC = 4.5 V, Vout = 0.1V or VCC − 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC = 4.5 V, Vin ≤ VT− min, /Iout/ ≤ 20µA, -55 to 25 °C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.98 | V | VCC = 4.5 V, Vin ≤ VT− min, /Iout/ ≤ 4.0mA, -55 to 25 °C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | VCC = 4.5 V, Vin ≤ VT− min, /Iout/ ≤ 4.0mA, ≤125 °C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC = 4.5 V, Vin ≥ VT+ max, /Iout/ ≤ 20µA, -55 to 25 °C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.26 | V | VCC = 4.5 V, Vin ≥ VT+ max, /Iout/ ≤ 4.0mA, -55 to 25 °C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | VCC = 4.5 V, Vin ≥ VT+ max, /Iout/ ≤ 4.0mA, ≤125 °C | 3 | ||
| Maximum Input Leakage Current | Iin | -0.1 | 0.1 | µA | Vin = VCC or GND, VCC = 6.0 V, -55 to 25 °C | 3 | |
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | Vin = VCC or GND, VCC = 6.0 V, ≤85 °C and ≤125 °C | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 1 | µA | Vin = VCC or GND, Iout = 0A, VCC = 6.0 V, -55 to 25 °C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 10 | µA | Vin = VCC or GND, Iout = 0A, VCC = 6.0 V, ≤85 °C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 40 | µA | Vin = VCC or GND, Iout = 0A, VCC = 6.0 V, ≤125 °C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 15 | ns | VCC = 4.5 V, -55 to 25 °C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 19 | ns | VCC = 4.5 V, ≤85 °C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 22 | ns | VCC = 4.5 V, ≤125 °C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 15 | ns | VCC = 4.5 V, -55 to 25 °C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 19 | ns | VCC = 4.5 V, ≤85 °C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 22 | ns | VCC = 4.5 V, ≤125 °C | 3 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 3 | |||
| Power Dissipation Capacitance (Per Inverter) | CPD | 22 | pF | Typical @ 25 °C, VCC = 5.0 V | 3 |
CAD (KiCad official)
- Symbol:
MC74HC14ADG - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74hc14adg-etched.step/mc74hc14adg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc14adg.step/mc74hc14adg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (11 pp, sha256
d847bd270a716f3a, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HC14ADG
**onsemi** · Inverters · SOIC-14
MC74HC14ADG from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Schmitt-trigger inverter 1 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 2 | Y1 | output | Inverter 1 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 3 | A2 | input | Schmitt-trigger inverter 2 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 4 | Y2 | output | Inverter 2 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 5 | A3 | input | Schmitt-trigger inverter 3 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 6 | Y3 | output | Inverter 3 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 7 | GND | power_in | Ground pin (0 V reference for supply and all logic levels). |
| 8 | Y4 | output | Inverter 4 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 9 | A4 | input | Schmitt-trigger inverter 4 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 10 | Y5 | output | Inverter 5 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 11 | A5 | input | Schmitt-trigger inverter 5 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 12 | Y6 | output | Inverter 6 output (Y = A inverted), drives 10 LSTTL loads; unused outputs must be left open. |
| 13 | A6 | input | Schmitt-trigger inverter 6 input with CMOS-level thresholds; input voltage 0 to VCC, and an unused input must be tied to GND or VCC. |
| 14 | VCC | power_in | Positive supply pin, operating range 2.0 to 6.0 V (absolute maximum 6.5 V) for MC74HC14A. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | | 6.5 | V | | 2 |
| DC Input Voltage | VIN | -0.5 | | | V | max is VCC + 0.5 | 2 |
| DC Output Voltage | VOUT | -0.5 | | | V | max is VCC + 0.5 | 2 |
| DC Input Current, per Pin | IIN | -20 | | 20 | mA | | 2 |
| DC Output Current, per Pin | IOUT | -25 | | 25 | mA | | 2 |
| DC Supply Current, VCC and GND Pins | ICC | -50 | | 50 | mA | | 2 |
| Input Clamp Current | IIK | -20 | | 20 | mA | VIN < 0 or VIN > VCC | 2 |
| Output Clamp Current | IOK | -20 | | 20 | mA | VOUT < 0 or VOUT > VCC | 2 |
| Storage Temperature | TSTG | -65 | | 150 | °C | | 2 |
| Lead Temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds | 2 |
| Junction Temperature Under Bias | TJ | -150 | | 150 | °C | | 2 |
| ESD Withstand Voltage, HBM | VESD | 4000 | | | V | Human Body Model | 2 |
| ESD Withstand Voltage, CDM | VESD | 1000 | | | V | Charged Device Model | 2 |
| Thermal Resistance | θJA | | | 116 | °C/W | SOIC-14 NB, FR4 board per JESD51-7 | 2 |
| Power Dissipation in Still Air | PD | | | 1077 | mW | SOIC-14 NB, at 25 °C | 2 |
| DC Supply Voltage (MC74HC) | VCC | 2 | | 6 | V | Referenced to GND | 2 |
| DC Input/Output Voltage (MC74HC) | VIN, VOUT | 0 | | | V | max is VCC; referenced to GND | 2 |
| Operating Free-Air Temperature | TA | -55 | | 125 | °C | MC74HC | 2 |
| Maximum Positive-Going Input Threshold Voltage | VT+ max | | | 3.15 | V | VCC = 4.5 V, Vout = 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 |
| Minimum Positive-Going Input Threshold Voltage | VT+ min | 2.3 | | | V | VCC = 4.5 V, Vout = 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 |
| Minimum Positive-Going Input Threshold Voltage | VT+ min | 2.25 | | | V | VCC = 4.5 V, Vout = 0.1V, /Iout/ ≤ 20µA, ≤125 °C | 3 |
| Maximum Negative-Going Input Threshold Voltage | VT− max | | | 2 | V | VCC = 4.5 V, Vout = VCC − 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 |
| Maximum Negative-Going Input Threshold Voltage | VT− max | | | 2.05 | V | VCC = 4.5 V, Vout = VCC − 0.1V, /Iout/ ≤ 20µA, ≤125 °C | 3 |
| Minimum Negative-Going Input Threshold Voltage | VT− min | 0.9 | | | V | VCC = 4.5 V, Vout = VCC − 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 |
| Maximum Hysteresis Voltage | VHmax | | | 2.25 | V | VCC = 4.5 V, Vout = 0.1V or VCC − 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 |
| Minimum Hysteresis Voltage | VHmin | 0.4 | | | V | VCC = 4.5 V, Vout = 0.1V or VCC − 0.1V, /Iout/ ≤ 20µA, -55 to 25 °C | 3 |
| Minimum High-Level Output Voltage | VOH | 4.4 | | | V | VCC = 4.5 V, Vin ≤ VT− min, /Iout/ ≤ 20µA, -55 to 25 °C | 3 |
| Minimum High-Level Output Voltage | VOH | 3.98 | | | V | VCC = 4.5 V, Vin ≤ VT− min, /Iout/ ≤ 4.0mA, -55 to 25 °C | 3 |
| Minimum High-Level Output Voltage | VOH | 3.7 | | | V | VCC = 4.5 V, Vin ≤ VT− min, /Iout/ ≤ 4.0mA, ≤125 °C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.1 | V | VCC = 4.5 V, Vin ≥ VT+ max, /Iout/ ≤ 20µA, -55 to 25 °C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.26 | V | VCC = 4.5 V, Vin ≥ VT+ max, /Iout/ ≤ 4.0mA, -55 to 25 °C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.4 | V | VCC = 4.5 V, Vin ≥ VT+ max, /Iout/ ≤ 4.0mA, ≤125 °C | 3 |
| Maximum Input Leakage Current | Iin | -0.1 | | 0.1 | µA | Vin = VCC or GND, VCC = 6.0 V, -55 to 25 °C | 3 |
| Maximum Input Leakage Current | Iin | -1 | | 1 | µA | Vin = VCC or GND, VCC = 6.0 V, ≤85 °C and ≤125 °C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 1 | µA | Vin = VCC or GND, Iout = 0A, VCC = 6.0 V, -55 to 25 °C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 10 | µA | Vin = VCC or GND, Iout = 0A, VCC = 6.0 V, ≤85 °C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 40 | µA | Vin = VCC or GND, Iout = 0A, VCC = 6.0 V, ≤125 °C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 15 | ns | VCC = 4.5 V, -55 to 25 °C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 19 | ns | VCC = 4.5 V, ≤85 °C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 22 | ns | VCC = 4.5 V, ≤125 °C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 15 | ns | VCC = 4.5 V, -55 to 25 °C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 19 | ns | VCC = 4.5 V, ≤85 °C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 22 | ns | VCC = 4.5 V, ≤125 °C | 3 |
| Maximum Input Capacitance | Cin | | | 10 | pF | | 3 |
| Power Dissipation Capacitance (Per Inverter) | CPD | | 22 | | pF | Typical @ 25 °C, VCC = 5.0 V | 3 |
## CAD (KiCad official)
- Symbol: `MC74HC14ADG`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `mc74hc14adg-etched.step` / `mc74hc14adg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hc14adg.step` / `mc74hc14adg.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hc14a-d.pdf) (11 pp, sha256 `d847bd270a716f3a`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hc14adg-datasheet.pdf)