component
MC74HC138ADTR2G
Public Made by Adomby adom
onsemi Signal Switches / Encoders & Decoders / Multiplexers, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+202−8@@ -1,13 +1,212 @@ {+ "schema_version": 1,+ "type": "component", "slug": "mc74hc138adtr2g",+ "title": "MC74HC138ADTR2G",+ "brief": "onsemi Signal Switches / Encoders & Decoders / Multiplexers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "onsemi Signal Switches / Encoders & Decoders / Multiplexers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "mc74hc138adtr2g" ],+ "component": {+ "mpn": "MC74HC138ADTR2G",+ "manufacturer": "onsemi",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Signal Switches / Encoders & Decoders / Multiplexers",+ "datasheet": "https://www.onsemi.com/pdf/datasheet/mc74hc138adtr2-d.pdf",+ "parts": {+ "symbol": "mc74hc138adtr2g.kicad_sym",+ "footprint": "mc74hc138adtr2g.kicad_mod",+ "model_3d": "mc74hc138adtr2g.glb",+ "model_3d_step": "mc74hc138adtr2g.step",+ "lbr": "mc74hc138adtr2g.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "A0",+ "type": "input",+ "description": "Address input bit 0. Together with A1 and A2, selects which of the eight Y outputs is driven low when the chip is enabled."+ },+ {+ "number": "2",+ "name": "A1",+ "type": "input",+ "description": "Address input bit 1. Together with A0 and A2, selects which of the eight Y outputs is driven low when the chip is enabled."+ },+ {+ "number": "3",+ "name": "A2",+ "type": "input",+ "description": "Address input bit 2. Together with A0 and A1, selects which of the eight Y outputs is driven low when the chip is enabled."+ },+ {+ "number": "4",+ "name": "CS2",+ "type": "input",+ "description": "Chip-select input 2 (active-low). Must be low, along with CS3 low and CS1 high, for the chip to be selected and outputs to follow the address inputs."+ },+ {+ "number": "5",+ "name": "CS3",+ "type": "input",+ "description": "Chip-select input 3 (active-low). Must be low, along with CS2 low and CS1 high, for the chip to be selected and outputs to follow the address inputs."+ },+ {+ "number": "6",+ "name": "CS1",+ "type": "input",+ "description": "Chip-select input 1 (active-high). Must be high, along with CS2 and CS3 low, for the chip to be selected and outputs to follow the address inputs."+ },+ {+ "number": "7",+ "name": "Y7",+ "type": "output",+ "description": "Active-low decoded output 7. Drives low when address A2A1A0=111 and the chip is selected; otherwise remains high."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). Return for VCC supply and all logic signals."+ },+ {+ "number": "9",+ "name": "Y6",+ "type": "output",+ "description": "Active-low decoded output 6. Drives low when address A2A1A0=110 and the chip is selected; otherwise remains high."+ },+ {+ "number": "10",+ "name": "Y5",+ "type": "output",+ "description": "Active-low decoded output 5. Drives low when address A2A1A0=101 and the chip is selected; otherwise remains high."+ },+ {+ "number": "11",+ "name": "Y4",+ "type": "output",+ "description": "Active-low decoded output 4. Drives low when address A2A1A0=100 and the chip is selected; otherwise remains high."+ },+ {+ "number": "12",+ "name": "Y3",+ "type": "output",+ "description": "Active-low decoded output 3. Drives low when address A2A1A0=011 and the chip is selected; otherwise remains high."+ },+ {+ "number": "13",+ "name": "Y2",+ "type": "output",+ "description": "Active-low decoded output 2. Drives low when address A2A1A0=010 and the chip is selected; otherwise remains high."+ },+ {+ "number": "14",+ "name": "Y1",+ "type": "output",+ "description": "Active-low decoded output 1. Drives low when address A2A1A0=001 and the chip is selected; otherwise remains high."+ },+ {+ "number": "15",+ "name": "Y0",+ "type": "output",+ "description": "Active-low decoded output 0. Drives low when address A2A1A0=000 and the chip is selected; otherwise remains high."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage, 2.0 V to 6.0 V (referenced to GND). Absolute maximum 7.0 V."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.onsemi.com/pdf/datasheet/mc74hc138adtr2-d.pdf",+ "pages": 10,+ "sha256": "12975c730cca4e3e",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "onsemi",+ "Package": "TSSOP-16",+ "Category": "Logic",+ "Pins": "16"+ }+ },+ "variants": [+ {+ "mpn": "MC74HC138ADTR2G",+ "kind": "packaging"+ },+ {+ "mpn": "MC74HC138ADTR2GNLV74HC138ADTR2G",+ "kind": "packaging"+ },+ {+ "mpn": "MC74HC138ADTR2GDG",+ "kind": "packaging"+ },+ {+ "mpn": "MC74HC138ADTR2GDR2G",+ "kind": "packaging"+ },+ {+ "mpn": "MC74HC138ADG",+ "kind": "unknown"+ },+ {+ "mpn": "MC74HC138ADR2G",+ "kind": "unknown"+ },+ {+ "mpn": "MC74HC138ADTR2GNLV74HC138ADR2G",+ "kind": "packaging"+ },+ {+ "mpn": "MC74HC138ADTR2GNG",+ "kind": "packaging"+ },+ {+ "mpn": "MC74HC138ANG",+ "kind": "unknown"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "mc74hc138adtr2g"+ ],+ "discovery_pitch": "MC74HC138ADTR2G (onsemi) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +224,5 @@ "docs/mc74hc138adtr2g-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }