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Ray mc74hc126adr2g: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b… 9428087 14d ago
{
  "schema_version": 1,
  "type": "component",
  "slug": "mc74hc126adr2g",
  "title": "MC74HC126ADR2G",
  "brief": "onsemi Buffer/Driver/Transceiver, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "mc74hc126adr2g"
  ],
  "component": {
    "mpn": "MC74HC126ADR2G",
    "manufacturer": "onsemi",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Buffer/Driver/Transceiver",
    "datasheet": "https://www.onsemi.com/pdf/datasheet/mc74hc126a-d.pdf",
    "parts": {
      "symbol": "mc74hc126adr2g.kicad_sym",
      "footprint": "mc74hc126adr2g.kicad_mod",
      "model_3d": "mc74hc126adr2g-etched.glb",
      "model_3d_plain": "mc74hc126adr2g.glb",
      "model_3d_step": "mc74hc126adr2g-etched.step",
      "model_3d_step_plain": "mc74hc126adr2g.step",
      "lbr": "mc74hc126adr2g.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "OE1",
        "type": "input",
        "description": "Active-high output enable for buffer 1. When high, output Y1 follows input A1; when low, Y1 is in high-impedance state."
      },
      {
        "number": "2",
        "name": "A1",
        "type": "input",
        "description": "Data input for buffer 1. CMOS-compatible logic input, buffered non-inverting to output Y1."
      },
      {
        "number": "3",
        "name": "Y1",
        "type": "tri_state",
        "description": "3-state noninverting buffer output 1. Drives up to 15 LSTTL loads; high-impedance when OE1 is low."
      },
      {
        "number": "4",
        "name": "OE2",
        "type": "input",
        "description": "Active-high output enable for buffer 2. When high, output Y2 follows input A2; when low, Y2 is in high-impedance state."
      },
      {
        "number": "5",
        "name": "A2",
        "type": "input",
        "description": "Data input for buffer 2. CMOS-compatible logic input, buffered non-inverting to output Y2."
      },
      {
        "number": "6",
        "name": "Y2",
        "type": "tri_state",
        "description": "3-state noninverting buffer output 2. Drives up to 15 LSTTL loads; high-impedance when OE2 is low."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V). Common return for supply and I/O."
      },
      {
        "number": "8",
        "name": "Y3",
        "type": "tri_state",
        "description": "3-state noninverting buffer output 3. Drives up to 15 LSTTL loads; high-impedance when OE3 is low."
      },
      {
        "number": "9",
        "name": "A3",
        "type": "input",
        "description": "Data input for buffer 3. CMOS-compatible logic input, buffered non-inverting to output Y3."
      },
      {
        "number": "10",
        "name": "OE3",
        "type": "input",
        "description": "Active-high output enable for buffer 3. When high, output Y3 follows input A3; when low, Y3 is in high-impedance state."
      },
      {
        "number": "11",
        "name": "Y4",
        "type": "tri_state",
        "description": "3-state noninverting buffer output 4. Drives up to 15 LSTTL loads; high-impedance when OE4 is low."
      },
      {
        "number": "12",
        "name": "A4",
        "type": "input",
        "description": "Data input for buffer 4. CMOS-compatible logic input, buffered non-inverting to output Y4."
      },
      {
        "number": "13",
        "name": "OE4",
        "type": "input",
        "description": "Active-high output enable for buffer 4. When high, output Y4 follows input A4; when low, Y4 is in high-impedance state."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage, 2.0 V to 6.0 V (absolute max 7.0 V). Bypass with a 0.1 uF ceramic capacitor close to the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.onsemi.com/pdf/datasheet/mc74hc126a-d.pdf",
        "pages": 9,
        "sha256": "7fc74019b728976b",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74HC126",
      "logic_family": "74HC",
      "function_code": "126",
      "function_class": "Buffer",
      "function_name": "Quad Bus Buffer with 3-State Outputs",
      "manufacturer": "Onsemi (Motorola legacy)",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "mc74hc126adr2g.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "mc74hc126adr2g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "624d2c0a24503b238c882d70787446426be853db223a328fadd9d9290abfda2f",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "onsemi",
      "Package": "SOIC-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "mc74hc126adr2g"
  ],
  "discovery_pitch": "MC74HC126ADR2G (onsemi) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "mc74hc126adr2g.kicad_sym",
    "mc74hc126adr2g.kicad_mod",
    "mc74hc126adr2g.glb",
    "mc74hc126adr2g.step",
    "mc74hc126adr2g-etched.step",
    "mc74hc126adr2g.lbr",
    "docs/hero.png",
    "docs/mc74hc126adr2g-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "MC74HC126ADG",
      "kind": "unknown"
    },
    {
      "mpn": "MC74HC126ADR2G",
      "kind": "packaging"
    },
    {
      "mpn": "MC74HC126ADR2GNLV74HC126ADR2G",
      "kind": "packaging"
    },
    {
      "mpn": "MC74HC126ADTR2G",
      "kind": "unknown"
    },
    {
      "mpn": "MC74HC126ADR2GNLV74HC126ADTR2G",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-28T18:51:30.757Z"
}