component
MC74HC125ADR2G
Public Made by Adomby adom
onsemi Buffers, Drivers, Receivers, Transceivers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HC125ADR2G
onsemi · Buffers, Drivers, Receivers, Transceivers · SOIC-14
MC74HC125ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Active-low output enable for buffer 1 (HC125A); when high, output Y1 is forced to the high-impedance state. |
| 2 | A1 | input | Data input of noninverting buffer 1; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 3 | Y1 | tri_state | Three-state noninverting buffer output 1, rated for 15 LSTTL loads and high impedance when OE1 is inactive. |
| 4 | OE2 | input | Active-low output enable for buffer 2 (HC125A); when high, output Y2 is forced to the high-impedance state. |
| 5 | A2 | input | Data input of noninverting buffer 2; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 6 | Y2 | tri_state | Three-state noninverting buffer output 2, rated for 15 LSTTL loads and high impedance when OE2 is inactive. |
| 7 | GND | power_in | Ground reference for all device voltages; all input and output voltages are referenced to this pin. |
| 8 | Y3 | tri_state | Three-state noninverting buffer output 3, rated for 15 LSTTL loads and high impedance when OE3 is inactive. |
| 9 | A3 | input | Data input of noninverting buffer 3; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 10 | OE3 | input | Active-low output enable for buffer 3 (HC125A); when high, output Y3 is forced to the high-impedance state. |
| 11 | Y4 | tri_state | Three-state noninverting buffer output 4, rated for 15 LSTTL loads and high impedance when OE4 is inactive. |
| 12 | A4 | input | Data input of noninverting buffer 4; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 13 | OE4 | input | Active-low output enable for buffer 4 (HC125A); when high, output Y4 is forced to the high-impedance state. |
| 14 | VCC | power_in | Positive supply, specified from 2.0 V to 6.0 V DC referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | Referenced to GND | 2 | |
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | Referenced to GND; upper limit printed as VCC | 2 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | °C | 2 | ||
| Input Rise and Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V (Figure 1) | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V (Figure 1) | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V (Figure 1) | 2 | |
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 2 | ||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 2 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | Per pin (printed as ±20 mA) | 2 | |
| DC Output Current, per Pin | Iout | -35 | 35 | mA | Per pin (printed as ±35 mA) | 2 | |
| DC Supply Current, VCC and GND Pins | ICC | -75 | 75 | mA | VCC and GND pins (printed as ±75 mA) | 2 | |
| Power Dissipation in Still Air | PD | 500 | mW | SOIC package, still air | 2 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 2 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds (SOIC or TSSOP package) | 2 | ||
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V; Vout = VCC, 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Input Voltage | VIH | 2.1 | V | VCC = 3.0 V; Vout = VCC, 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC = 4.5 V; Vout = VCC, 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | VCC = 6.0 V; Vout = VCC, 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | VCC = 3.0 V; Vout = 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | V | VCC = 2.0 V; Vin = VIH; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC = 4.5 V; Vin = VIH; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.9 | V | VCC = 6.0 V; Vin = VIH; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 2.2 | V | VCC = 3.0 V; Vin = VIH; /Iout/ ≤ 3.6 mA (125 °C column) | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | VCC = 4.5 V; Vin = VIH; /Iout/ ≤ 6.0 mA (125 °C column) | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.2 | V | VCC = 6.0 V; Vin = VIH; /Iout/ ≤ 7.8 mA (125 °C column) | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC = 2.0 V; Vin = VIL; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | VCC = 3.0 V; Vin = VIL; /Iout/ ≤ 3.6 mA (125 °C column) | 3 | ||
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | VCC = 6.0 V; Vin = VCC or GND (125 °C column) | 3 | |
| Maximum Three-State Leakage Current | IOZ | -10 | 10 | µA | VCC = 6.0 V; output high-impedance; Vin = VIL or VIH; Vout = VCC or GND (125 °C column) | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | µA | VCC = 6.0 V; Vin = VCC or GND; Iout = 0 µA (125 °C column) | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 135 | ns | VCC = 2.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 60 | ns | VCC = 3.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 27 | ns | VCC = 4.5 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 23 | ns | VCC = 6.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Output Enable to Y | tPLZ, tPHZ | 180 | ns | VCC = 2.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Output Enable to Y | tPLZ, tPHZ | 80 | ns | VCC = 3.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Output Enable to Y | tPLZ, tPHZ | 36 | ns | VCC = 4.5 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Output Enable to Y | tPLZ, tPHZ | 31 | ns | VCC = 6.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Output Enable to Y | tPZL, tPZH | 135 | ns | VCC = 2.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Output Enable to Y | tPZL, tPZH | 60 | ns | VCC = 3.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Output Enable to Y | tPZL, tPZH | 27 | ns | VCC = 4.5 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Propagation Delay, Output Enable to Y | tPZL, tPZH | 23 | ns | VCC = 6.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 90 | ns | VCC = 2.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 34 | ns | VCC = 3.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 18 | ns | VCC = 4.5 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 15 | ns | VCC = 6.0 V; CL = 50 pF (125 °C column) | 3 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 3 | |||
| Maximum 3-State Output Capacitance | Cout | 15 | pF | Output in high-impedance state | 3 |
CAD (KiCad official)
- Symbol:
MC74HC125ADR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74hc125adr2g-etched.step/mc74hc125adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc125adr2g.step/mc74hc125adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (7 pp, sha256
816414a92d397621, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).