component
MC74HC112ADR2G
Public Made by Adomby adom
onsemi Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HC112ADR2G
onsemi · Flip Flops · SOIC-16
MC74HC112ADR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLOCK 1 | input | Clock input for flip-flop 1; each flip-flop is negative-edge clocked, so it responds to the falling edge of this input. |
| 2 | K1 | input | J-K data input for flip-flop 1, sampled on the negative clock edge per the function table. |
| 3 | J1 | input | J data input for flip-flop 1, sampled on the negative clock edge per the function table. |
| 4 | SET 1 | input | Active-low asynchronous Set input for flip-flop 1; when Set and Reset are both low, both outputs remain low, but the output states are unpredictable if Set and Reset go high simultaneously. |
| 5 | Q1 | output | Flip-flop 1 true output. |
| 6 | Q1 (bar) | output | Flip-flop 1 complementary output. |
| 7 | Q2 (bar) | output | Flip-flop 2 complementary output. |
| 8 | GND | power_in | Ground reference for the device (Pin 8 = GND); all voltages are referenced to this pin. |
| 9 | Q2 | output | Flip-flop 2 true output. |
| 10 | SET 2 | input | Active-low asynchronous Set input for flip-flop 2; when Set and Reset are both low, both outputs remain low, but the output states are unpredictable if Set and Reset go high simultaneously. |
| 11 | J2 | input | J data input for flip-flop 2, sampled on the negative clock edge per the function table. |
| 12 | K2 | input | J-K data input for flip-flop 2, sampled on the negative clock edge per the function table. |
| 13 | CLOCK 2 | input | Clock input for flip-flop 2; each flip-flop is negative-edge clocked, so it responds to the falling edge of this input. |
| 14 | RESET 2 | input | Active-low asynchronous Reset input for flip-flop 2, which forces Q2 low when asserted. |
| 15 | RESET 1 | input | Active-low asynchronous Reset input for flip-flop 1, which forces Q1 low when asserted. |
| 16 | VCC | power_in | Positive supply pin; the recommended DC supply range is 2.0 V to 6.0 V referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | 3 | ||
| DC Input Voltage (Referenced to GND), max VCC + 1.5 V | Vin | -1.5 | V | 3 | |||
| DC Output Voltage (Referenced to GND), max VCC + 0.5 V | Vout | -0.5 | V | 3 | |||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | 3 | ||
| DC Output Current, per Pin | Iout | -25 | 25 | mA | 3 | ||
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | 3 | ||
| Power Dissipation in Still Air, SOIC Package | PD | 500 | mW | SOIC package | 3 | ||
| Storage Temperature | Tstg | -65 | 150 | C | 3 | ||
| Lead Temperature, 1 mm from case for 10 seconds (SOIC or TSSOP) | TL | 260 | C | 1 mm from case, 10 s | 3 | ||
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | 3 | ||
| DC Input Voltage, Output Voltage (Referenced to GND), max VCC | Vin, Vout | 0 | V | 3 | |||
| Operating Temperature, All Package Types | TA | -55 | 125 | C | 3 | ||
| Input Rise and Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V (Figure 1) | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V (Figure 1) | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V (Figure 1) | 3 | |
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA | 3 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC = 4.5 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA | 3 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | VCC = 6.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.3 | V | VCC = 2.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | VCC = 4.5 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.2 | V | VCC = 6.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ <= 20 uA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ <= 20 uA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.9 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ <= 20 uA | 3 | ||
| Minimum High-Level Output Voltage (125 C column) | VOH | 3.7 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ <= 4.0 mA; 125 C | 3 | ||
| Minimum High-Level Output Voltage (125 C column) | VOH | 5.2 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ <= 5.2 mA; 125 C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ <= 20 uA | 3 | ||
| Maximum Low-Level Output Voltage (125 C column) | VOL | 0.4 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ <= 4.0 mA; 125 C | 3 | ||
| Maximum Input Leakage Current (125 C column) | Iin | -1 | 1 | uA | VCC = 6.0 V; Vin = VCC or GND; 125 C | 3 | |
| Maximum Quiescent Supply Current, per package (125 C column) | ICC | 80 | uA | VCC = 6.0 V; Vin = VCC or GND; Iout = 0 uA; 125 C | 3 | ||
| Maximum Clock Frequency (50% duty cycle) (125 C column) | fmax | 4 | MHz | VCC = 2.0 V; CL = 50 pF; Figures 1 and 4; 125 C | 4 | ||
| Maximum Clock Frequency (50% duty cycle) (125 C column) | fmax | 20 | MHz | VCC = 4.5 V; CL = 50 pF; Figures 1 and 4; 125 C | 4 | ||
| Maximum Clock Frequency (50% duty cycle) (125 C column) | fmax | 24 | MHz | VCC = 6.0 V; CL = 50 pF; Figures 1 and 4; 125 C | 4 | ||
| Maximum Propagation Delay, Clock to Q or Q-bar (125 C column) | tPLH, tPHL | 190 | ns | VCC = 2.0 V; CL = 50 pF; Figures 1 and 4; 125 C | 4 | ||
| Maximum Propagation Delay, Clock to Q or Q-bar (125 C column) | tPLH, tPHL | 38 | ns | VCC = 4.5 V; CL = 50 pF; Figures 1 and 4; 125 C | 4 | ||
| Maximum Propagation Delay, Clock to Q or Q-bar (125 C column) | tPLH, tPHL | 32 | ns | VCC = 6.0 V; CL = 50 pF; Figures 1 and 4; 125 C | 4 | ||
| Maximum Propagation Delay, Reset to Q or Q-bar (125 C column) | tPLH, tPHL | 235 | ns | VCC = 2.0 V; CL = 50 pF; Figures 2 and 4; 125 C | 4 | ||
| Maximum Propagation Delay, Reset to Q or Q-bar (125 C column) | tPLH, tPHL | 47 | ns | VCC = 4.5 V; CL = 50 pF; Figures 2 and 4; 125 C | 4 | ||
| Maximum Propagation Delay, Reset to Q or Q-bar (125 C column) | tPLH, tPHL | 40 | ns | VCC = 6.0 V; CL = 50 pF; Figures 2 and 4; 125 C | 4 | ||
| Maximum Propagation Delay, Set to Q or Q-bar (125 C column) | tPLH, tPHL | 250 | ns | VCC = 2.0 V; CL = 50 pF; Figures 2 and 4; 125 C | 4 | ||
| Maximum Propagation Delay, Set to Q or Q-bar (125 C column) | tPLH, tPHL | 50 | ns | VCC = 4.5 V; CL = 50 pF; Figures 2 and 4; 125 C | 4 | ||
| Maximum Propagation Delay, Set to Q or Q-bar (125 C column) | tPLH, tPHL | 43 | ns | VCC = 6.0 V; CL = 50 pF; Figures 2 and 4; 125 C | 4 | ||
| Maximum Output Transition Time, Any Output (125 C column) | tTLH, tTHL | 110 | ns | VCC = 2.0 V; CL = 50 pF; Figures 1 and 4; 125 C | 4 | ||
| Maximum Output Transition Time, Any Output (125 C column) | tTLH, tTHL | 22 | ns | VCC = 4.5 V; CL = 50 pF; Figures 1 and 4; 125 C | 4 | ||
| Maximum Output Transition Time, Any Output (125 C column) | tTLH, tTHL | 19 | ns | VCC = 6.0 V; CL = 50 pF; Figures 1 and 4; 125 C | 4 | ||
| Minimum Setup Time, J or K to Clock (125 C column) | tsu | 150 | ns | VCC = 2.0 V; Figure 3; 125 C | 4 | ||
| Minimum Setup Time, J or K to Clock (125 C column) | tsu | 30 | ns | VCC = 4.5 V; Figure 3; 125 C | 4 | ||
| Minimum Setup Time, J or K to Clock (125 C column) | tsu | 26 | ns | VCC = 6.0 V; Figure 3; 125 C | 4 | ||
| Minimum Hold Time, Clock to J or K | th | 3 | ns | VCC = 2.0 V; Figure 3 | 4 | ||
| Minimum Recovery Time, Set or Reset Inactive to Clock (125 C column) | trec | 150 | ns | VCC = 2.0 V; Figure 2; 125 C | 4 | ||
| Minimum Recovery Time, Set or Reset Inactive to Clock (125 C column) | trec | 30 | ns | VCC = 4.5 V; Figure 2; 125 C | 4 | ||
| Minimum Recovery Time, Set or Reset Inactive to Clock (125 C column) | trec | 26 | ns | VCC = 6.0 V; Figure 2; 125 C | 4 | ||
| Minimum Pulse Width, Clock (125 C column) | tw | 120 | ns | VCC = 2.0 V; Figure 1; 125 C | 4 | ||
| Minimum Pulse Width, Clock (125 C column) | tw | 24 | ns | VCC = 4.5 V; Figure 1; 125 C | 4 | ||
| Minimum Pulse Width, Clock (125 C column) | tw | 20 | ns | VCC = 6.0 V; Figure 1; 125 C | 4 |
CAD (KiCad official)
- Symbol:
MC74HC112ADR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hc112adr2g-etched.step/mc74hc112adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc112adr2g.step/mc74hc112adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (8 pp, sha256
6b3a076d6c84258e, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).