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MC74HC03ADR2G

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onsemi Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74HC03ADR2G

onsemi · Logic Gates · SOIC-14

MC74HC03ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Data input A of NAND gate 1; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC.
2 B1 input Data input B of NAND gate 1; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC.
3 Y1 output Open-drain NAND output of gate 1 that needs an external pullup resistor; output current is limited to ±25 mA per pin.
4 A2 input Data input A of NAND gate 2; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC.
5 B2 input Data input B of NAND gate 2; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC.
6 Y2 output Open-drain NAND output of gate 2 that needs an external pullup resistor; output current is limited to ±25 mA per pin.
7 GND power_in Ground reference for all voltages (0 V); DC supply voltage is specified referenced to GND.
8 Y3 output Open-drain NAND output of gate 3 that needs an external pullup resistor; output current is limited to ±25 mA per pin.
9 A3 input Data input A of NAND gate 3; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC.
10 B3 input Data input B of NAND gate 3; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC.
11 Y4 output Open-drain NAND output of gate 4 that needs an external pullup resistor; output current is limited to ±25 mA per pin.
12 A4 input Data input A of NAND gate 4; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC.
13 B4 input Data input B of NAND gate 4; inputs must stay between GND and VCC, and unused inputs must be tied to GND or VCC.
14 VCC power_in Positive supply, specified from 2.0 V to 6.0 V referenced to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-Level Input Voltage (VCC = 2.0 V) VIH 1.5 V Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
High-Level Input Voltage (VCC = 3.0 V) VIH 2.1 V Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
High-Level Input Voltage (VCC = 4.5 V) VIH 3.15 V Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
High-Level Input Voltage (VCC = 6.0 V) VIH 4.2 V Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
Low-Level Input Voltage (VCC = 2.0 V) VIL 0.5 V Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
Low-Level Input Voltage (VCC = 3.0 V) VIL 0.9 V Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
Low-Level Input Voltage (VCC = 4.5 V) VIL 1.35 V Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
Low-Level Input Voltage (VCC = 6.0 V) VIL 1.8 V Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
Maximum Low-Level Output Voltage (VCC = 2.0 V) VOL 0.1 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
Maximum Low-Level Output Voltage (VCC = 4.5 V) VOL 0.1 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
Maximum Low-Level Output Voltage (VCC = 6.0 V) VOL 0.1 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; guaranteed limit ≤125°C column 3
Maximum Low-Level Output Voltage (VCC = 3.0 V) VOL 0.4 V Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; guaranteed limit ≤125°C column 3
Maximum Low-Level Output Voltage (VCC = 4.5 V) VOL 0.4 V Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; guaranteed limit ≤125°C column 3
Maximum Low-Level Output Voltage (VCC = 6.0 V) VOL 0.4 V Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; guaranteed limit ≤125°C column 3
Maximum Input Leakage Current (VCC = 6.0 V) Iin -1 1 µA Vin = VCC or GND; guaranteed limit ≤125°C column 3
Maximum Quiescent Supply Current (per Package, VCC = 6.0 V) ICC 40 µA Vin = VCC or GND; Iout = 0 A; guaranteed limit ≤125°C column 3
Maximum Three-State Leakage Current (VCC = 6.0 V) IOZ -10 10 µA Output in high-impedance state; Vin = VIL or VIH; Vout = VCC or GND; guaranteed limit ≤125°C column 3
Maximum Propagation Delay, Input A or B to Output Y (VCC = 2.0 V) tPLZ, tPZL 180 ns CL = 50 pF, input tr = tf = 6 ns (Figures 1 and 2); ≤125°C column 3
Maximum Propagation Delay, Input A or B to Output Y (VCC = 3.0 V) tPLZ, tPZL 75 ns CL = 50 pF, input tr = tf = 6 ns (Figures 1 and 2); ≤125°C column 3
Maximum Propagation Delay, Input A or B to Output Y (VCC = 4.5 V) tPLZ, tPZL 36 ns CL = 50 pF, input tr = tf = 6 ns (Figures 1 and 2); ≤125°C column 3
Maximum Propagation Delay, Input A or B to Output Y (VCC = 6.0 V) tPLZ, tPZL 31 ns CL = 50 pF, input tr = tf = 6 ns (Figures 1 and 2); ≤125°C column 3
Maximum Output Transition Time, Any Output (VCC = 2.0 V) tTLH, tTHL 110 ns CL = 50 pF, input tr = tf = 6 ns (Figures 1 and 2); ≤125°C column 3
Maximum Output Transition Time, Any Output (VCC = 3.0 V) tTLH, tTHL 36 ns CL = 50 pF, input tr = tf = 6 ns (Figures 1 and 2); ≤125°C column 3
Maximum Output Transition Time, Any Output (VCC = 4.5 V) tTLH, tTHL 22 ns CL = 50 pF, input tr = tf = 6 ns (Figures 1 and 2); ≤125°C column 3
Maximum Output Transition Time, Any Output (VCC = 6.0 V) tTLH, tTHL 19 ns CL = 50 pF, input tr = tf = 6 ns (Figures 1 and 2); ≤125°C column 3
Maximum Input Capacitance Cin 10 pF 3
Maximum Three-State Output Capacitance Cout 10 pF Output in high-impedance state 3
DC Supply Voltage (Referenced to GND) VCC 2 6 V 2
DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout 0 V Maximum printed as VCC 2
Operating Temperature, All Package Types TA -55 125 °C 2
Input Rise and Fall Time (VCC = 2.0 V) tr, tf 0 1000 ns Figure 1 2
Input Rise and Fall Time (VCC = 4.5 V) tr, tf 0 500 ns Figure 1 2
Input Rise and Fall Time (VCC = 6.0 V) tr, tf 0 400 ns Figure 1 2
DC Supply Voltage (Referenced to GND) VCC -0.5 7 V Referenced to GND 2
DC Input Voltage (Referenced to GND) Vin -0.5 V Maximum printed as VCC + 0.5 2
DC Output Voltage (Referenced to GND) Vout -0.5 V Maximum printed as VCC + 0.5 2
DC Input Current, per Pin Iin -20 20 mA 2
DC Output Current, per Pin Iout -25 25 mA 2
DC Supply Current, VCC and GND Pins ICC -50 50 mA 2
Power Dissipation in Still Air, SOIC Package PD 500 mW SOIC package; derating −7 mW/°C from 65° to 125°C 2
Storage Temperature Tstg -65 150 °C 2
Lead Temperature TL 260 °C 1 mm from case for 10 seconds, SOIC or TSSOP package 2

CAD (KiCad official)

  • Symbol: MC74HC03ADR2G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: mc74hc03adr2g-etched.step / mc74hc03adr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hc03adr2g.step / mc74hc03adr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 95961b9f2052ae4c, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF