component
MC74ACT373DWR2G
Public Made by Adomby adom
onsemi Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownMC74ACT373DWR2G
onsemi · Latches · SOIC-20-300mil
MC74ACT373DWR2G from onsemi, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Output Enable input; LOW enables the 3-state outputs, HIGH puts them in high impedance without blocking entry of new data into the latches. |
| 2 | O0 | tri_state | 3-state latch output 0, sources/sinks 24 mA. |
| 3 | D0 | input | Data input 0; ACT version has TTL-compatible inputs. |
| 4 | D1 | input | Data input 1; ACT version has TTL-compatible inputs. |
| 5 | O1 | tri_state | 3-state latch output 1, sources/sinks 24 mA. |
| 6 | O2 | tri_state | 3-state latch output 2, sources/sinks 24 mA. |
| 7 | D2 | input | Data input 2; ACT version has TTL-compatible inputs. |
| 8 | D3 | input | Data input 3; ACT version has TTL-compatible inputs. |
| 9 | O3 | tri_state | 3-state latch output 3, sources/sinks 24 mA. |
| 10 | GND | power_in | Ground reference (0 V) for supply and I/O voltages. |
| 11 | LE | input | Latch Enable input; HIGH makes latches transparent, LOW latches data that met setup time. |
| 12 | O4 | tri_state | 3-state latch output 4, sources/sinks 24 mA. |
| 13 | D4 | input | Data input 4; ACT version has TTL-compatible inputs. |
| 14 | D5 | input | Data input 5; ACT version has TTL-compatible inputs. |
| 15 | O5 | tri_state | 3-state latch output 5, sources/sinks 24 mA. |
| 16 | O6 | tri_state | 3-state latch output 6, sources/sinks 24 mA. |
| 17 | D6 | input | Data input 6; ACT version has TTL-compatible inputs. |
| 18 | D7 | input | Data input 7; ACT version has TTL-compatible inputs. |
| 19 | O7 | tri_state | 3-state latch output 7, sources/sinks 24 mA. |
| 20 | VCC | power_in | Supply voltage; ACT operates 4.5 V to 5.5 V (absolute max -0.5 to +7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-20-300mil |
| Category | Logic ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 7 | V | Referenced to GND | 3 | |
| DC Input Voltage | VIN | -0.5 | V | -0.5 to VCC +0.5 | 3 | ||
| DC Input Diode Current | IIK | -20 | 20 | mA | 3 | ||
| DC Output Diode Current | IOK | -50 | 50 | mA | 3 | ||
| DC Output Sink/Source Current | IOUT | -50 | 50 | mA | 3 | ||
| DC Supply Current, per Output Pin | ICC | -50 | 50 | mA | 3 | ||
| DC Ground Current, per Output Pin | IGND | -100 | 100 | mA | 3 | ||
| Storage Temperature Range | TSTG | 65 | 150 | C | minimum printed as 65 (sign lost in text) | 3 | |
| Junction Temperature Under Bias | TJ | 140 | C | 3 | |||
| Thermal Resistance, SOIC | θJA | 65.8 | C/W | SOIC, JESD 51-7 | 3 | ||
| Supply Voltage 'ACT | VCC | 4.5 | 5 | 5.5 | V | 'ACT | 3 |
| Operating Ambient Temperature Range | TA | -40 | 25 | 85 | °C | 3 | |
| Output Current - High | IOH | -24 | mA | 3 | |||
| Output Current - Low | IOL | 24 | mA | 3 | |||
| Input Rise and Fall Time 'ACT | tr, tf | 10 | ns/V | VCC @ 4.5 V, VIN 0.8 V to 2.0 V | 3 | ||
| Input Rise and Fall Time 'ACT | tr, tf | 8 | ns/V | VCC @ 5.5 V, VIN 0.8 V to 2.0 V | 3 | ||
| Min High Level Input Voltage | VIH | 2 | 1.5 | V | VCC 4.5 V, TA -40 to +85°C; VOUT = 0.1 V or VCC - 0.1 V | 6 | |
| Max Low Level Input Voltage | VIL | 1.5 | 0.8 | V | VCC 4.5 V, TA -40 to +85°C; VOUT = 0.1 V or VCC - 0.1 V | 6 | |
| Min High Level Output Voltage | VOH | 4.4 | 4.49 | V | VCC 4.5 V, IOUT = -50 µA, TA -40 to +85°C | 6 | |
| Min High Level Output Voltage | VOH | 5.4 | 5.49 | V | VCC 5.5 V, IOUT = -50 µA, TA -40 to +85°C | 6 | |
| Min High Level Output Voltage | VOH | 3.76 | V | VCC 4.5 V, IOH -24 mA, VIN = VIL or VIH, TA -40 to +85°C | 6 | ||
| Min High Level Output Voltage | VOH | 4.76 | V | VCC 5.5 V, IOH -24 mA, VIN = VIL or VIH, TA -40 to +85°C | 6 | ||
| Max Low Level Output Voltage | VOL | 0.001 | 0.1 | V | VCC 4.5 V, IOUT = 50 µA, TA -40 to +85°C | 6 | |
| Max Low Level Output Voltage | VOL | 0.44 | V | VCC 4.5 V, IOL 24 mA, VIN = VIL or VIH, TA -40 to +85°C | 6 | ||
| Max Input Leakage Current | IIN | -1 | 1 | µA | VCC 5.5 V, VI = VCC, GND, TA -40 to +85°C | 6 | |
| Additional Max. ICC/Input | ICCT | 0.6 | 1.5 | mA | VCC 5.5 V, VI = VCC - 2.1 V | 6 | |
| Max 3-State Current | IOZ | -5 | 5 | µA | VCC 5.5 V, VI(OE) = VIL, VIH; VI = VCC, GND; VO = VCC, GND; TA -40 to +85°C | 6 | |
| Min Dynamic Output Current | IOLD | 75 | mA | VCC 5.5 V, VOLD = 1.65 V Max | 6 | ||
| Min Dynamic Output Current | IOHD | -75 | mA | VCC 5.5 V, VOHD = 3.85 V Min | 6 | ||
| Max Quiescent Supply Current | ICC | 8 | 80 | µA | VCC 5.5 V, VIN = VCC or GND, TA -40 to +85°C | 6 | |
| Propagation Delay Dn to On (tPLH) | tPLH | 1.5 | 8.5 | 11.5 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 |
| Propagation Delay Dn to On (tPHL) | tPHL | 1.5 | 8 | 11.5 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 |
| Propagation Delay LE to On (tPLH) | tPLH | 2 | 8.5 | 11.5 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 |
| Propagation Delay LE to On (tPHL) | tPHL | 1.5 | 8 | 11.5 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 |
| Output Enable Time | tPZH | 1.5 | 8 | 10.5 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 |
| Output Enable Time | tPZL | 1.5 | 7.5 | 10.5 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 |
| Output Disable Time | tPHZ | 2.5 | 9 | 12.5 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 |
| Output Disable Time | tPLZ | 1 | 7.5 | 10 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 |
| Setup Time, HIGH or LOW Dn to LE | ts | 8 | 3 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 | |
| Hold Time, HIGH or LOW Dn to LE | th | 1 | 0 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 | |
| LE Pulse Width, HIGH | tw | 8 | 2 | ns | VCC 5.0 V, CL = 50 pF, TA -40 to +85°C | 7 | |
| Input Capacitance | CIN | 4.5 | pF | VCC = 5.0 V | 7 | ||
| Power Dissipation Capacitance | CPD | 40 | pF | VCC = 5.0 V | 7 |
CAD (KiCad official)
- Symbol:
MC74ACT373DWR2G - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
mc74act373dwr2g-etched.step/mc74act373dwr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74act373dwr2g.step/mc74act373dwr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (11 pp, sha256
de6eab515b94bb37, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).