component
MC74AC14DR2G
Public Made by Adomby adom
onsemi Inverters, SOIC-14. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74AC14DR2G
onsemi · Inverters · SOIC-14
MC74AC14DR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I1 | input | Schmitt-trigger input of inverter 1 (CMOS levels for AC, TTL levels for ACT). |
| 2 | O1 | output | Output of inverter 1, sources/sinks 24 mA. |
| 3 | I2 | input | Schmitt-trigger input of inverter 2 (CMOS levels for AC, TTL levels for ACT). |
| 4 | O2 | output | Output of inverter 2, sources/sinks 24 mA. |
| 5 | I3 | input | Schmitt-trigger input of inverter 3 (CMOS levels for AC, TTL levels for ACT). |
| 6 | O3 | output | Output of inverter 3, sources/sinks 24 mA. |
| 7 | GND | power_in | Ground, 0 V reference for supply, inputs and outputs. |
| 8 | O4 | output | Output of inverter 4, sources/sinks 24 mA. |
| 9 | I4 | input | Schmitt-trigger input of inverter 4 (CMOS levels for AC, TTL levels for ACT). |
| 10 | O5 | output | Output of inverter 5, sources/sinks 24 mA. |
| 11 | I5 | input | Schmitt-trigger input of inverter 5 (CMOS levels for AC, TTL levels for ACT). |
| 12 | O6 | output | Output of inverter 6, sources/sinks 24 mA. |
| 13 | I6 | input | Schmitt-trigger input of inverter 6 (CMOS levels for AC, TTL levels for ACT). |
| 14 | VCC | power_in | Positive supply, 2.0 V to 6.0 V recommended for AC (absolute maximum 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum Positive Threshold (VCC 3.0 V) | Vt+ | 2.2 | V | VCC 3.0 V; TA = worst case; 74AC column | 4 | ||
| Maximum Positive Threshold (VCC 4.5 V) | Vt+ | 3.2 | V | VCC 4.5 V; TA = worst case; 74AC column | 4 | ||
| Maximum Positive Threshold (VCC 5.5 V) | Vt+ | 3.9 | V | VCC 5.5 V; TA = worst case; 74AC column | 4 | ||
| Minimum Negative Threshold (VCC 3.0 V) | Vt- | 0.5 | V | VCC 3.0 V; TA = worst case; 74AC column | 4 | ||
| Minimum Negative Threshold (VCC 4.5 V) | Vt- | 0.9 | V | VCC 4.5 V; TA = worst case; 74AC column | 4 | ||
| Minimum Negative Threshold (VCC 5.5 V) | Vt- | 1.1 | V | VCC 5.5 V; TA = worst case; 74AC column | 4 | ||
| Maximum Hysteresis (VCC 3.0 V) | Vh(max) | 1.2 | V | VCC 3.0 V; TA = worst case; 74AC column | 4 | ||
| Maximum Hysteresis (VCC 4.5 V) | Vh(max) | 1.4 | V | VCC 4.5 V; TA = worst case; 74AC column | 4 | ||
| Maximum Hysteresis (VCC 5.5 V) | Vh(max) | 1.6 | V | VCC 5.5 V; TA = worst case; 74AC column | 4 | ||
| Minimum Hysteresis (VCC 3.0 V) | Vh(min) | 0.3 | V | VCC 3.0 V; TA = worst case; 74AC column | 4 | ||
| Minimum Hysteresis (VCC 4.5 V) | Vh(min) | 0.4 | V | VCC 4.5 V; TA = worst case; 74AC column | 4 | ||
| Minimum Hysteresis (VCC 5.5 V) | Vh(min) | 0.5 | V | VCC 5.5 V; TA = worst case; 74AC column | 4 | ||
| Minimum High Level Output Voltage (VCC 3.0 V) | VOH | 2.9 | 2.99 | V | VCC 3.0 V; IOUT = -50 µA; TA -40 to +85 °C | 3 | |
| Minimum High Level Output Voltage (VCC 4.5 V) | VOH | 4.4 | 4.49 | V | VCC 4.5 V; IOUT = -50 µA; TA -40 to +85 °C | 3 | |
| Minimum High Level Output Voltage (VCC 5.5 V) | VOH | 5.4 | 5.49 | V | VCC 5.5 V; IOUT = -50 µA; TA -40 to +85 °C | 3 | |
| Minimum High Level Output Voltage (VCC 3.0 V, 12 mA) | VOH | 2.46 | V | VCC 3.0 V; VIN = VIL or VIH; IOH = -12 mA; TA -40 to +85 °C | 3 | ||
| Minimum High Level Output Voltage (VCC 4.5 V, 24 mA) | VOH | 3.76 | V | VCC 4.5 V; VIN = VIL or VIH; IOH = -24 mA; TA -40 to +85 °C | 3 | ||
| Minimum High Level Output Voltage (VCC 5.5 V, 24 mA) | VOH | 4.76 | V | VCC 5.5 V; VIN = VIL or VIH; IOH = -24 mA; TA -40 to +85 °C | 3 | ||
| Maximum Low Level Output Voltage (VCC 3.0 V) | VOL | 0.002 | 0.1 | V | VCC 3.0 V; IOUT = 50 µA; TA -40 to +85 °C | 3 | |
| Maximum Low Level Output Voltage (VCC 4.5 V) | VOL | 0.001 | 0.1 | V | VCC 4.5 V; IOUT = 50 µA; TA -40 to +85 °C | 3 | |
| Maximum Low Level Output Voltage (VCC 5.5 V) | VOL | 0.001 | 0.1 | V | VCC 5.5 V; IOUT = 50 µA; TA -40 to +85 °C | 3 | |
| Maximum Low Level Output Voltage (VCC 3.0 V, 12 mA) | VOL | 0.44 | V | VCC 3.0 V; VIN = VIL or VIH; IOL = 12 mA; TA -40 to +85 °C | 3 | ||
| Maximum Low Level Output Voltage (VCC 4.5 V, 24 mA) | VOL | 0.44 | V | VCC 4.5 V; VIN = VIL or VIH; IOL = 24 mA; TA -40 to +85 °C | 3 | ||
| Maximum Low Level Output Voltage (VCC 5.5 V, 24 mA) | VOL | 0.44 | V | VCC 5.5 V; VIN = VIL or VIH; IOL = 24 mA; TA -40 to +85 °C | 3 | ||
| Maximum Input Leakage Current | IIN | -1 | 0.1 | 1 | µA | VCC 5.5 V; VI = VCC, GND | 3 |
| Minimum Dynamic Output Current (low) | IOLD | 75 | mA | VCC 5.5 V; VOLD = 1.65 V max; max test 2.0 ms | 3 | ||
| Minimum Dynamic Output Current (high) | IOHD | -75 | mA | VCC 5.5 V; VOHD = 3.85 V min; max test 2.0 ms | 3 | ||
| Maximum Quiescent Supply Current | ICC | 4 | 40 | µA | VCC 5.5 V; VIN = VCC or GND; TA -40 to +85 °C | 3 | |
| Propagation Delay tPLH (VCC 3.3 V, TA +25 °C) | tPLH | 1.5 | 9.5 | 13.5 | ns | VCC 3.3 V ±0.3 V; CL = 50 pF; TA +25 °C; figs 3-5 | 3 |
| Propagation Delay tPLH (VCC 3.3 V, TA -40 to +85 °C) | tPLH | 1.5 | 15 | ns | VCC 3.3 V ±0.3 V; CL = 50 pF; TA -40 to +85 °C; figs 3-5 | 3 | |
| Propagation Delay tPLH (VCC 5.0 V, TA +25 °C) | tPLH | 1.5 | 7 | 10 | ns | VCC 5.0 V ±0.5 V; CL = 50 pF; TA +25 °C; figs 3-5 | 3 |
| Propagation Delay tPLH (VCC 5.0 V, TA -40 to +85 °C) | tPLH | 1.5 | 11 | ns | VCC 5.0 V ±0.5 V; CL = 50 pF; TA -40 to +85 °C; figs 3-5 | 3 | |
| Propagation Delay tPHL (VCC 3.3 V, TA +25 °C) | tPHL | 1.5 | 7.5 | 11.5 | ns | VCC 3.3 V ±0.3 V; CL = 50 pF; TA +25 °C; figs 3-5 | 3 |
| Propagation Delay tPHL (VCC 3.3 V, TA -40 to +85 °C) | tPHL | 1.5 | 13 | ns | VCC 3.3 V ±0.3 V; CL = 50 pF; TA -40 to +85 °C; figs 3-5 | 3 | |
| Propagation Delay tPHL (VCC 5.0 V, TA +25 °C) | tPHL | 1.5 | 6 | 8.5 | ns | VCC 5.0 V ±0.5 V; CL = 50 pF; TA +25 °C; figs 3-5 | 3 |
| Propagation Delay tPHL (VCC 5.0 V, TA -40 to +85 °C) | tPHL | 1.5 | 9.5 | ns | VCC 5.0 V ±0.5 V; CL = 50 pF; TA -40 to +85 °C; figs 3-5 | 3 | |
| Supply Voltage (′AC) | VCC | 2 | 5 | 6 | V | ′AC devices | 2 |
| DC Input Voltage, Output Voltage (Ref. to GND) | Vin, Vout | 0 | V | Referenced to GND; maximum printed as VCC (not numeric) | 2 | ||
| Operating Ambient Temperature Range | TA | -40 | 25 | 85 | °C | 2 | |
| Output Current - High | IOH | -24 | mA | 2 | |||
| Output Current - Low | IOL | 24 | mA | 2 | |||
| DC Supply Voltage | VCC | -0.5 | 7 | V | 2 | ||
| DC Input Diode Current | IIK | 20 | mA | 2 | |||
| DC Output Diode Current | IOK | 50 | mA | 2 | |||
| DC Output Sink/Source Current | IO | 50 | mA | 2 | |||
| DC Supply Current per Output Pin | ICC | 50 | mA | 2 | |||
| DC Ground Current per Output Pin | IGND | 50 | mA | 2 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 2 | ||
| Junction Temperature under Bias | TJ | 150 | °C | Under bias | 2 | ||
| Thermal Resistance, Junction to Ambient (SOIC) | θJA | 125 | °C/W | SOIC package; JESD51-7 | 2 | ||
| Power Dissipation in Still Air at 85°C (SOIC) | PD | 125 | mW | SOIC; still air; 85°C | 2 | ||
| ESD Withstand Voltage, Human Body Model | VESD | 2000 | V | Human Body Model; printed as > 2000 | 2 | ||
| ESD Withstand Voltage, Machine Model | VESD | 200 | V | Machine Model; printed as > 200 | 2 | ||
| ESD Withstand Voltage, Charged Device Model | VESD | 1000 | V | Charged Device Model; printed as > 1000 | 2 | ||
| Latch-Up Performance | ILatch-Up | 100 | mA | Above VCC and below GND at 85°C | 2 |
CAD (KiCad official)
- Symbol:
MC74AC14DR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74ac14dr2g-etched.step/mc74ac14dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74ac14dr2g.step/mc74ac14dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (7 pp, sha256
b946d8ea03cd5fea, retrieved 2026-10-21, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).