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MC74AC138DTR2G

onsemi · Signal Switches, Multiplexers, Decoders · TSSOP-16

MC74AC138DTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Address input A0, the least significant of the three binary-weighted address inputs (A0-A2) that select one of eight active-LOW outputs.
2 A1 input Address input A1, one of three binary-weighted address inputs (A0-A2) that select one of eight active-LOW outputs.
3 A2 input Address input A2, the most significant of the three binary-weighted address inputs (A0-A2) that select one of eight active-LOW outputs.
4 E1 input Active-LOW enable input; all outputs stay HIGH unless E1 and E2 are LOW and E3 is HIGH.
5 E2 input Active-LOW enable input; all outputs stay HIGH unless E1 and E2 are LOW and E3 is HIGH.
6 E3 input Active-HIGH enable input; all outputs stay HIGH unless E1 and E2 are LOW and E3 is HIGH.
7 O7 output Active-LOW mutually exclusive output 7 that sources/sinks 24 mA, driven LOW only when the address is 111 and the device is enabled.
8 GND power_in Ground pin (0 V reference) for the supply.
9 O6 output Active-LOW mutually exclusive output 6 that sources/sinks 24 mA, driven LOW only when the address is 110 and the device is enabled.
10 O5 output Active-LOW mutually exclusive output 5 that sources/sinks 24 mA, driven LOW only when the address is 101 and the device is enabled.
11 O4 output Active-LOW mutually exclusive output 4 that sources/sinks 24 mA, driven LOW only when the address is 100 and the device is enabled.
12 O3 output Active-LOW mutually exclusive output 3 that sources/sinks 24 mA, driven LOW only when the address is 011 and the device is enabled.
13 O2 output Active-LOW mutually exclusive output 2 that sources/sinks 24 mA, driven LOW only when the address is 010 and the device is enabled.
14 O1 output Active-LOW mutually exclusive output 1 that sources/sinks 24 mA, driven LOW only when the address is 001 and the device is enabled.
15 O0 output Active-LOW mutually exclusive output 0 that sources/sinks 24 mA, driven LOW only when the address is 000 and the device is enabled.
16 VCC power_in Positive supply; recommended 2.0 V to 6.0 V for 'AC and 4.5 V to 5.5 V for 'ACT, absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input High Level Voltage VIH 2.1 1.5 V VCC=3.0 V; VOUT=0.1 V or VCC-0.1 V 5
Input High Level Voltage VIH 3.15 2.25 V VCC=4.5 V; VOUT=0.1 V or VCC-0.1 V 5
Input High Level Voltage VIH 3.85 2.75 V VCC=5.5 V; VOUT=0.1 V or VCC-0.1 V 5
Input Low Level Voltage VIL 1.5 0.9 V VCC=3.0 V; VOUT=0.1 V or VCC-0.1 V 5
Input Low Level Voltage VIL 2.25 1.35 V VCC=4.5 V; VOUT=0.1 V or VCC-0.1 V 5
Input Low Level Voltage VIL 2.75 1.65 V VCC=5.5 V; VOUT=0.1 V or VCC-0.1 V 5
Minimum High Level Output Voltage VOH 2.9 2.99 V VCC=3.0 V; IOUT=-50 uA 5
Minimum High Level Output Voltage VOH 4.4 4.49 V VCC=4.5 V; IOUT=-50 uA 5
Minimum High Level Output Voltage VOH 5.4 5.49 V VCC=5.5 V; IOUT=-50 uA 5
Minimum High Level Output Voltage VOH 2.46 V VCC=3.0 V; VIN=VIL or VIH; IOH=-12 mA 5
Minimum High Level Output Voltage VOH 3.76 V VCC=4.5 V; VIN=VIL or VIH; IOH=-24 mA 5
Minimum High Level Output Voltage VOH 4.76 V VCC=5.5 V; VIN=VIL or VIH; IOH=-24 mA 5
Maximum Low Level Output Voltage VOL 0.002 0.1 V VCC=3.0 V; IOUT=50 uA 5
Maximum Low Level Output Voltage VOL 0.001 0.1 V VCC=4.5 V; IOUT=50 uA 5
Maximum Low Level Output Voltage VOL 0.44 V VCC=3.0 V; VIN=VIL or VIH; IOL=12 mA 5
Maximum Input Leakage Current IIN -1 1 uA VI = VCC, GND 5
Minimum Dynamic Output Current IOLD 75 mA VOLD = 1.65 V Max 5
Minimum Dynamic Output Current IOHD -75 mA VOHD = 3.85 V Min 5
Maximum Quiescent Supply Current ICC 80 uA VCC=5.5 V; VIN = VCC or GND 5
Propagation Delay An to On (tPLH) tPLH 1.5 8.5 15 ns VCC=3.3 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay An to On (tPLH) tPLH 1.5 6.5 10.5 ns VCC=5.0 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay An to On (tPHL) tPHL 1.5 8 14 ns VCC=3.3 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay An to On (tPHL) tPHL 1.5 6 10.5 ns VCC=5.0 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay E1 or E2 to On (tPLH) tPLH 1.5 11 16 ns VCC=3.3 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay E1 or E2 to On (tPLH) tPLH 1.5 8 12 ns VCC=5.0 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay E1 or E2 to On (tPHL) tPHL 1.5 9.5 15 ns VCC=3.3 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay E1 or E2 to On (tPHL) tPHL 1.5 7 10.5 ns VCC=5.0 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay E3 to On (tPLH) tPLH 1.5 11 16.5 ns VCC=3.3 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay E3 to On (tPLH) tPLH 1.5 8 12.5 ns VCC=5.0 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay E3 to On (tPHL) tPHL 1.5 8.5 14 ns VCC=3.3 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
Propagation Delay E3 to On (tPHL) tPHL 1 6 9.5 ns VCC=5.0 V; CL=50 pF; TA=-40 to +85 C; Fig 3-6 5
DC Supply Voltage (AC) VCC 2 5 6 V 'AC devices 4
Operating Ambient Temperature Range TA -40 25 85 °C 4
Junction Temperature (PDIP) TJ 140 °C PDIP as printed 4
Output Current High IOH -24 mA 4
Output Current Low IOL 24 mA 4
Input Rise and Fall Time (AC, non-Schmitt) tr, tf 150 ns/V VCC @ 3.0 V 4
Input Rise and Fall Time (AC, non-Schmitt) tr, tf 40 ns/V VCC @ 4.5 V 4
Input Rise and Fall Time (AC, non-Schmitt) tr, tf 25 ns/V VCC @ 5.5 V 4
DC Supply Voltage VCC -0.5 7 V 4
DC Input Voltage VI -0.5 V -0.5 V to VCC+0.5 V 4
DC Output Voltage VO -0.5 V Note 1; -0.5 V to VCC+0.5 V 4
DC Input Diode Current IIK 20 mA 4
DC Output Diode Current IOK 50 mA 4
DC Output Sink/Source Current IO 50 mA 4
DC Supply Current per Output Pin ICC 50 mA 4
DC Ground Current per Output Pin IGND 50 mA 4
Storage Temperature Range TSTG -65 150 °C 4
Lead Temperature TL 260 °C 1 mm from case for 10 seconds 4
Junction Temperature under Bias TJ 150 °C 4
ESD Withstand Voltage Human Body Model VESD 2000 V HBM; printed as > 2000 V 4
Latch-Up Performance ILatch-Up 100 mA Above VCC and below GND at 85°C 4
Thermal Resistance Junction-to-Ambient JA 103.8 °C/W TSSOP package; JESD51-7 4
Power Dissipation in Still Air at 65°C PD 500 mW TSSOP package; still air at 65°C 4

CAD (KiCad official)

  • Symbol: MC74AC138DTR2G
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: mc74ac138dtr2g-etched.step / mc74ac138dtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74ac138dtr2g.step / mc74ac138dtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (10 pp, sha256 88a716fef04e65ac, retrieved 2026-10-20, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF