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MC74AC05DR2G

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onsemi Inverters, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74AC05DR2G

onsemi · Inverters · SOIC-14

MC74AC05DR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Input of inverter 1 (Y1 is its open-drain output); the datasheet states the AC inputs are CMOS-compatible and, with pullup resistors, TTL-compatible, and input voltage is limited to -0.5 V to VCC + 0.5 V.
2 Y1 output Open-drain output of inverter 1 (Z = high impedance when input is H), rated for 24 mA sink and requiring an external pullup.
3 A2 input Input of inverter 2 (Y2 is its open-drain output); the datasheet states the AC inputs are CMOS-compatible and, with pullup resistors, TTL-compatible, and input voltage is limited to -0.5 V to VCC + 0.5 V.
4 Y2 output Open-drain output of inverter 2 (Z = high impedance when input is H), rated for 24 mA sink and requiring an external pullup.
5 A3 input Input of inverter 3 (Y3 is its open-drain output); the datasheet states the AC inputs are CMOS-compatible and, with pullup resistors, TTL-compatible, and input voltage is limited to -0.5 V to VCC + 0.5 V.
6 Y3 output Open-drain output of inverter 3 (Z = high impedance when input is H), rated for 24 mA sink and requiring an external pullup.
7 GND power_in Ground reference for the device (PIN 7 = GND per the datasheet).
8 Y4 output Open-drain output of inverter 4 (Z = high impedance when input is H), rated for 24 mA sink and requiring an external pullup.
9 A4 input Input of inverter 4 (Y4 is its open-drain output); the datasheet states the AC inputs are CMOS-compatible and, with pullup resistors, TTL-compatible, and input voltage is limited to -0.5 V to VCC + 0.5 V.
10 Y5 output Open-drain output of inverter 5 (Z = high impedance when input is H), rated for 24 mA sink and requiring an external pullup.
11 A5 input Input of inverter 5 (Y5 is its open-drain output); the datasheet states the AC inputs are CMOS-compatible and, with pullup resistors, TTL-compatible, and input voltage is limited to -0.5 V to VCC + 0.5 V.
12 Y6 output Open-drain output of inverter 6 (Z = high impedance when input is H), rated for 24 mA sink and requiring an external pullup.
13 A6 input Input of inverter 6 (Y6 is its open-drain output); the datasheet states the AC inputs are CMOS-compatible and, with pullup resistors, TTL-compatible, and input voltage is limited to -0.5 V to VCC + 0.5 V.
14 VCC power_in Supply pin; VCC is 2.0 V to 6.0 V for 74AC and 4.5 V to 5.5 V for 74ACT devices per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Supply Voltage (′AC) VCC 2 5 6 V ′AC devices 2
DC Regulated Power Voltage (Ref. to GND) VREG 0 V Referenced to GND; upper limit is VCC 2
Input Rise and Fall Time, ′AC except Schmitt inputs, VCC @ 3.0 V tr, tf 150 ns/V Vin from 30% to 70% VCC 2
Input Rise and Fall Time, ′AC except Schmitt inputs, VCC @ 4.5 V tr, tf 40 ns/V Vin from 30% to 70% VCC 2
Input Rise and Fall Time, ′AC except Schmitt inputs, VCC @ 5.5 V tr, tf 25 ns/V Vin from 30% to 70% VCC 2
Operating Ambient Temperature Range TA -40 25 85 °C 2
Output Current − HIGH IOH -24 mA 2
Output Current − LOW IOL 24 mA 2
DC Supply Voltage VCC -0.5 7 V 2
DC Input Voltage VI -0.5 V −0.5 ≤ VI ≤ VCC + 0.5 V 2
DC Output Voltage (Note 1) VO -0.5 V −0.5 ≤ VO ≤ VCC + 0.5 V 2
DC Input Diode Current IIK 20 mA 2
DC Output Diode Current IOK 50 mA 2
DC Output Sink/Source Current IO 50 mA 2
DC Supply Current per Output Pin ICC 50 mA 2
DC Ground Current per Output Pin IGND 50 mA 2
Storage Temperature Range TSTG -65 150 °C 2
Lead Temperature TL 260 °C 1 mm from case for 10 seconds 2
Junction Temperature under Bias TJ 150 °C 2
ESD Withstand Voltage, Human Body Model VESD 2000 V Human Body Model (Note 3); printed as > 2000 2
ESD Withstand Voltage, Machine Model VESD 200 V Machine Model (Note 4); printed as > 200 2
ESD Withstand Voltage, Charged Device Model VESD 1000 V Charged Device Model (Note 5); printed as > 1000 2
Latch-Up Performance ILatch-Up 100 mA Above VCC and below GND at 85°C (Note 6) 2
Power Dissipation in Still Air at 85°C, SOIC PD 125 mW SOIC package; still air, TA = 85°C 2
Minimum High Level Input Voltage, 74AC, VCC 3.0 V VIH 2.1 1.5 V VOUT = 0.1 V or VCC − 0.1 V; TA = −40°C to +85°C 3
Minimum High Level Input Voltage, 74AC, VCC 4.5 V VIH 3.15 2.25 V VOUT = 0.1 V or VCC − 0.1 V; TA = −40°C to +85°C 3
Minimum High Level Input Voltage, 74AC, VCC 5.5 V VIH 3.85 2.75 V VOUT = 0.1 V or VCC − 0.1 V; TA = −40°C to +85°C 3
Maximum Low Level Input Voltage, 74AC, VCC 3.0 V VIL 1.5 0.9 V VOUT = 0.1 V or VCC − 0.1 V; TA = −40°C to +85°C 3
Maximum Low Level Input Voltage, 74AC, VCC 4.5 V VIL 2.25 1.35 V VOUT = 0.1 V or VCC − 0.1 V; TA = −40°C to +85°C 3
Maximum Low Level Input Voltage, 74AC, VCC 5.5 V VIL 2.75 1.65 V VOUT = 0.1 V or VCC − 0.1 V; TA = −40°C to +85°C 3
Maximum Low Level Output Voltage, VCC 3.0 V VOL 0.002 0.1 V IOUT = 50 µA; TA = −40°C to +85°C 3
Maximum Low Level Output Voltage, VCC 4.5 V VOL 0.001 0.1 V IOUT = 50 µA; TA = −40°C to +85°C 3
Maximum Low Level Output Voltage, VCC 5.5 V VOL 0.001 0.1 V IOUT = 50 µA; TA = −40°C to +85°C 3
Maximum Low Level Output Voltage, VCC 3.0 V, IOL 12 mA VOL 0.44 V VIN = VIL or VIH; IOL = 12 mA; TA = −40°C to +85°C 3
Maximum Low Level Output Voltage, VCC 4.5 V, IOL 24 mA VOL 0.44 V VIN = VIL or VIH; IOL = 24 mA; TA = −40°C to +85°C 3
Maximum Low Level Output Voltage, VCC 5.5 V, IOL 24 mA VOL 0.44 V VIN = VIL or VIH; IOL = 24 mA; TA = −40°C to +85°C 3
Maximum Input Leakage Current, VCC 5.5 V IIN -1 1 µA VI = VCC, GND; TA = −40°C to +85°C 3
Minimum Dynamic Output Current (LOW), VCC 5.5 V IOLD 75 mA VOLD = 1.65 V Max; max test duration 2.0 ms, one output loaded at a time 3
Minimum Dynamic Output Current (HIGH), VCC 5.5 V IOHD -75 mA VOHD = 3.85 V Min; max test duration 2.0 ms, one output loaded at a time 3
Maximum Quiescent Supply Current, VCC 5.5 V ICC 40 µA VIN = VCC or GND; TA = −40°C to +85°C 3
Propagation Delay Output Enable (tPZL), VCC 3.3 V tPZL 1 9 ns VCC = 3.3 V ±0.3 V; CL = 50 pF; TA = −40°C to +85°C 3
Propagation Delay Output Enable (tPZL), VCC 5.0 V tPZL 1 6.5 ns VCC = 5.0 V ±0.5 V; CL = 50 pF; TA = −40°C to +85°C 3
Propagation Delay Output Enable (tPLZ), VCC 3.3 V tPLZ 1 9 ns VCC = 3.3 V ±0.3 V; CL = 50 pF; TA = −40°C to +85°C 3
Propagation Delay Output Enable (tPLZ), VCC 5.0 V tPLZ 1 6.5 ns VCC = 5.0 V ±0.5 V; CL = 50 pF; TA = −40°C to +85°C 3
Input Capacitance CIN 4.5 pF VCC = 5.0 V 4
Power Dissipation Capacitance CPD 30 pF VCC = 5.0 V 4
Thermal Resistance, Junction-to-Ambient, SOIC JA 125 °C/W SOIC package; per JESD51-7 (Note 2) 2

CAD (KiCad official)

  • Symbol: MC74AC05DR2G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: mc74ac05dr2g-etched.step / mc74ac05dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74ac05dr2g.step / mc74ac05dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 59c3f1b0cc219b20, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF