component
MC74AC00DTR2G
Public Made by Adomby adom
onsemi Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MC74AC00DTR2G
onsemi · Logic Gates · TSSOP-14
MC74AC00DTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Data input A of NAND gate 1 (Y1 = A1·B1); DC input voltage is specified from GND to VCC. |
| 2 | B1 | input | Data input B of NAND gate 1 (Y1 = A1·B1); DC input voltage is specified from GND to VCC. |
| 3 | Y1 | output | Output of NAND gate 1 (Y1 = A1·B1); output sink/source current is limited to 24 mA (IOL/IOH) in the recommended operating conditions. |
| 4 | A2 | input | Data input A of NAND gate 2 (Y2 = A2·B2); DC input voltage is specified from GND to VCC. |
| 5 | B2 | input | Data input B of NAND gate 2 (Y2 = A2·B2); DC input voltage is specified from GND to VCC. |
| 6 | Y2 | output | Output of NAND gate 2 (Y2 = A2·B2); output sink/source current is limited to 24 mA (IOL/IOH) in the recommended operating conditions. |
| 7 | GND | power_in | Ground reference for the device (PIN 7 = GND per the logic diagram). |
| 8 | Y3 | output | Output of NAND gate 3 (Y3 = A3·B3); output sink/source current is limited to 24 mA (IOL/IOH) in the recommended operating conditions. |
| 9 | A3 | input | Data input A of NAND gate 3 (Y3 = A3·B3); DC input voltage is specified from GND to VCC. |
| 10 | B3 | input | Data input B of NAND gate 3 (Y3 = A3·B3); DC input voltage is specified from GND to VCC. |
| 11 | Y4 | output | Output of NAND gate 4 (Y4 = A4·B4); output sink/source current is limited to 24 mA (IOL/IOH) in the recommended operating conditions. |
| 12 | A4 | input | Data input A of NAND gate 4 (Y4 = A4·B4); DC input voltage is specified from GND to VCC. |
| 13 | B4 | input | Data input B of NAND gate 4 (Y4 = A4·B4); DC input voltage is specified from GND to VCC. |
| 14 | VCC | power_in | Positive supply; the AC00 part is rated 2.0 V to 6.0 V (recommended operating range 2.0 V to 6.0 V, 5.0 V typical). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 7 | V | 2 | ||
| DC Input Voltage | VI | -0.5 | V | Upper limit printed as VCC + 0.5 V | 2 | ||
| DC Output Voltage | VO | -0.5 | V | Upper limit printed as VCC + 0.5 V (Note 1) | 2 | ||
| DC Input Diode Current | IIK | 20 | mA | 2 | |||
| DC Output Diode Current | IOK | 50 | mA | 2 | |||
| DC Output Sink/Source Current | IO | 50 | mA | 2 | |||
| DC Supply Current per Output Pin | ICC | 50 | mA | 2 | |||
| DC Ground Current per Output Pin | IGND | 50 | mA | 2 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 2 | ||
| Junction Temperature under Bias | TJ | 150 | °C | Under bias | 2 | ||
| Thermal Resistance (TSSOP) | JA | 170 | °C/W | TSSOP package; per JESD51-7 | 2 | ||
| Power Dissipation in Still Air at 85°C (TSSOP) | PD | 170 | mW | TSSOP package; still air at 85°C | 2 | ||
| ESD Withstand Voltage, Human Body Model | VESD | 2000 | V | Human Body Model; EIA/JESD22-A114-A (printed as > 2000) | 2 | ||
| ESD Withstand Voltage, Machine Model | VESD | 200 | V | Machine Model; EIA/JESD22-A115-A (printed as > 200) | 2 | ||
| ESD Withstand Voltage, Charged Device Model | VESD | 1000 | V | Charged Device Model; JESD22-C101-A (printed as > 1000) | 2 | ||
| Latch-Up Performance | 100 | mA | Above VCC and below GND at 85°C; EIA/JESD78 | 2 | |||
| Supply Voltage (MC74AC00) | VCC | 2 | 5 | 6 | V | MC74AC00 | 2 |
| DC Input Voltage, Output Voltage (Ref. to GND) | Vin, Vout | 0 | V | Referenced to GND; upper limit printed as VCC | 2 | ||
| Input Rise and Fall Time (Note 7), VCC @ 3.0 V | tr, tf | 150 | ns/V | VCC @ 3.0 V; Vin from 30% to 70% VCC (Note 7) | 2 | ||
| Input Rise and Fall Time (Note 7), VCC @ 4.5 V | tr, tf | 40 | ns/V | VCC @ 4.5 V; Vin from 30% to 70% VCC (Note 7) | 2 | ||
| Input Rise and Fall Time (Note 7), VCC @ 5.5 V | tr, tf | 25 | ns/V | VCC @ 5.5 V; Vin from 30% to 70% VCC (Note 7) | 2 | ||
| Junction Temperature | TJ | 150 | °C | 2 | |||
| Operating Ambient Temperature Range | TA | -55 | 25 | 125 | °C | 2 | |
| Output Current High | IOH | -24 | mA | 2 | |||
| Output Current Low | IOL | 24 | mA | 2 | |||
| Minimum High Level Input Voltage, VCC 3.0 V | VIH | 2.1 | 1.5 | V | VCC = 3.0 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 | |
| Minimum High Level Input Voltage, VCC 4.5 V | VIH | 3.15 | 2.25 | V | VCC = 4.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 | |
| Minimum High Level Input Voltage, VCC 5.5 V | VIH | 3.85 | 2.75 | V | VCC = 5.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 | |
| Maximum Low Level Input Voltage, VCC 3.0 V | VIL | 1.5 | 0.9 | V | VCC = 3.0 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 | |
| Maximum Low Level Input Voltage, VCC 4.5 V | VIL | 2.25 | 1.35 | V | VCC = 4.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 | |
| Maximum Low Level Input Voltage, VCC 5.5 V | VIL | 2.75 | 1.65 | V | VCC = 5.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 | |
| Minimum High Level Output Voltage, VCC 3.0 V | VOH | 2.9 | 2.99 | V | VCC = 3.0 V; IOUT = −50 µA; TA = −55 °C to +125 °C | 3 | |
| Minimum High Level Output Voltage, VCC 4.5 V | VOH | 4.4 | 4.49 | V | VCC = 4.5 V; IOUT = −50 µA; TA = −55 °C to +125 °C | 3 | |
| Minimum High Level Output Voltage, VCC 5.5 V | VOH | 5.4 | 5.49 | V | VCC = 5.5 V; IOUT = −50 µA; TA = −55 °C to +125 °C | 3 | |
| Minimum High Level Output Voltage, VCC 3.0 V, IOH −12 mA | VOH | 2.4 | 2.56 | V | *VIN = VIL or VIH; IOH = −12 mA; TA = −55 °C to +125 °C | 3 | |
| Minimum High Level Output Voltage, VCC 4.5 V, IOH −24 mA | VOH | 3.7 | 3.86 | V | *VIN = VIL or VIH; IOH = −24 mA; TA = −55 °C to +125 °C | 3 | |
| Minimum High Level Output Voltage, VCC 5.5 V, IOH −24 mA | VOH | 4.7 | 4.86 | V | *VIN = VIL or VIH; IOH = −24 mA; TA = −55 °C to +125 °C | 3 | |
| Maximum Low Level Output Voltage, VCC 3.0 V | VOL | 0.002 | 0.1 | V | VCC = 3.0 V; IOUT = 50 µA; TA = −55 °C to +125 °C | 3 | |
| Maximum Low Level Output Voltage, VCC 4.5 V | VOL | 0.001 | 0.1 | V | VCC = 4.5 V; IOUT = 50 µA; TA = −55 °C to +125 °C | 3 | |
| Maximum Low Level Output Voltage, VCC 5.5 V | VOL | 0.001 | 0.1 | V | VCC = 5.5 V; IOUT = 50 µA; TA = −55 °C to +125 °C | 3 | |
| Maximum Low Level Output Voltage, VCC 3.0 V, IOL 12 mA | VOL | 0.36 | 0.5 | V | *VIN = VIL or VIH; IOL = 12 mA; TA = −55 °C to +125 °C | 3 | |
| Maximum Low Level Output Voltage, VCC 4.5 V, IOL 24 mA | VOL | 0.36 | 0.5 | V | *VIN = VIL or VIH; IOL = 24 mA; TA = −55 °C to +125 °C | 3 | |
| Maximum Low Level Output Voltage, VCC 5.5 V, IOL 24 mA | VOL | 0.36 | 0.5 | V | *VIN = VIL or VIH; IOL = 24 mA; TA = −55 °C to +125 °C | 3 | |
| Maximum Input Leakage Current | IIN | 0.1 | 1 | µA | VCC = 5.5 V; VI = VCC, GND; TA = −55 °C to +125 °C | 3 | |
| Minimum Dynamic Output Current (sink) | IOLD | 50 | mA | VCC = 5.5 V; VOLD = 1.65 V Max; one output loaded at a time, max 2.0 ms | 3 | ||
| Minimum Dynamic Output Current (source) | IOHD | -50 | mA | VCC = 5.5 V; VOHD = 3.85 V Min; one output loaded at a time, max 2.0 ms | 3 | ||
| Maximum Quiescent Supply Current | ICC | 4 | 40 | µA | VCC = 5.5 V; VIN = VCC or GND; TA = −55 °C to +125 °C | 3 | |
| Propagation Delay tPLH, VCC 3.3 V | tPLH | 1 | 7 | 11 | ns | VCC = 3.3 V; CL = 50 pF; tr = tf = 3.0 ns; TA = −55 °C to +125 °C | 3 |
| Propagation Delay tPLH, VCC 5.0 V | tPLH | 1 | 6 | 8.5 | ns | VCC = 5.0 V; CL = 50 pF; tr = tf = 3.0 ns; TA = −55 °C to +125 °C | 3 |
| Propagation Delay tPHL, VCC 3.3 V | tPHL | 1 | 5.5 | 9 | ns | VCC = 3.3 V; CL = 50 pF; tr = tf = 3.0 ns; TA = −55 °C to +125 °C | 3 |
| Propagation Delay tPHL, VCC 5.0 V | tPHL | 1 | 4.5 | 7 | ns | VCC = 5.0 V; CL = 50 pF; tr = tf = 3.0 ns; TA = −55 °C to +125 °C | 3 |
CAD (KiCad official)
- Symbol:
MC74AC00DTR2G - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
mc74ac00dtr2g-etched.step/mc74ac00dtr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74ac00dtr2g.step/mc74ac00dtr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (9 pp, sha256
3de93c5e45a21247, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74AC00DTR2G
**onsemi** · Logic Gates · TSSOP-14
MC74AC00DTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Data input A of NAND gate 1 (Y1 = A1·B1); DC input voltage is specified from GND to VCC. |
| 2 | B1 | input | Data input B of NAND gate 1 (Y1 = A1·B1); DC input voltage is specified from GND to VCC. |
| 3 | Y1 | output | Output of NAND gate 1 (Y1 = A1·B1); output sink/source current is limited to 24 mA (IOL/IOH) in the recommended operating conditions. |
| 4 | A2 | input | Data input A of NAND gate 2 (Y2 = A2·B2); DC input voltage is specified from GND to VCC. |
| 5 | B2 | input | Data input B of NAND gate 2 (Y2 = A2·B2); DC input voltage is specified from GND to VCC. |
| 6 | Y2 | output | Output of NAND gate 2 (Y2 = A2·B2); output sink/source current is limited to 24 mA (IOL/IOH) in the recommended operating conditions. |
| 7 | GND | power_in | Ground reference for the device (PIN 7 = GND per the logic diagram). |
| 8 | Y3 | output | Output of NAND gate 3 (Y3 = A3·B3); output sink/source current is limited to 24 mA (IOL/IOH) in the recommended operating conditions. |
| 9 | A3 | input | Data input A of NAND gate 3 (Y3 = A3·B3); DC input voltage is specified from GND to VCC. |
| 10 | B3 | input | Data input B of NAND gate 3 (Y3 = A3·B3); DC input voltage is specified from GND to VCC. |
| 11 | Y4 | output | Output of NAND gate 4 (Y4 = A4·B4); output sink/source current is limited to 24 mA (IOL/IOH) in the recommended operating conditions. |
| 12 | A4 | input | Data input A of NAND gate 4 (Y4 = A4·B4); DC input voltage is specified from GND to VCC. |
| 13 | B4 | input | Data input B of NAND gate 4 (Y4 = A4·B4); DC input voltage is specified from GND to VCC. |
| 14 | VCC | power_in | Positive supply; the AC00 part is rated 2.0 V to 6.0 V (recommended operating range 2.0 V to 6.0 V, 5.0 V typical). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | | 7 | V | | 2 |
| DC Input Voltage | VI | -0.5 | | | V | Upper limit printed as VCC + 0.5 V | 2 |
| DC Output Voltage | VO | -0.5 | | | V | Upper limit printed as VCC + 0.5 V (Note 1) | 2 |
| DC Input Diode Current | IIK | | | 20 | mA | | 2 |
| DC Output Diode Current | IOK | | | 50 | mA | | 2 |
| DC Output Sink/Source Current | IO | | | 50 | mA | | 2 |
| DC Supply Current per Output Pin | ICC | | | 50 | mA | | 2 |
| DC Ground Current per Output Pin | IGND | | | 50 | mA | | 2 |
| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 2 |
| Lead Temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds | 2 |
| Junction Temperature under Bias | TJ | | | 150 | °C | Under bias | 2 |
| Thermal Resistance (TSSOP) | JA | | 170 | | °C/W | TSSOP package; per JESD51-7 | 2 |
| Power Dissipation in Still Air at 85°C (TSSOP) | PD | | | 170 | mW | TSSOP package; still air at 85°C | 2 |
| ESD Withstand Voltage, Human Body Model | VESD | 2000 | | | V | Human Body Model; EIA/JESD22-A114-A (printed as > 2000) | 2 |
| ESD Withstand Voltage, Machine Model | VESD | 200 | | | V | Machine Model; EIA/JESD22-A115-A (printed as > 200) | 2 |
| ESD Withstand Voltage, Charged Device Model | VESD | 1000 | | | V | Charged Device Model; JESD22-C101-A (printed as > 1000) | 2 |
| Latch-Up Performance | | | | 100 | mA | Above VCC and below GND at 85°C; EIA/JESD78 | 2 |
| Supply Voltage (MC74AC00) | VCC | 2 | 5 | 6 | V | MC74AC00 | 2 |
| DC Input Voltage, Output Voltage (Ref. to GND) | Vin, Vout | 0 | | | V | Referenced to GND; upper limit printed as VCC | 2 |
| Input Rise and Fall Time (Note 7), VCC @ 3.0 V | tr, tf | | | 150 | ns/V | VCC @ 3.0 V; Vin from 30% to 70% VCC (Note 7) | 2 |
| Input Rise and Fall Time (Note 7), VCC @ 4.5 V | tr, tf | | | 40 | ns/V | VCC @ 4.5 V; Vin from 30% to 70% VCC (Note 7) | 2 |
| Input Rise and Fall Time (Note 7), VCC @ 5.5 V | tr, tf | | | 25 | ns/V | VCC @ 5.5 V; Vin from 30% to 70% VCC (Note 7) | 2 |
| Junction Temperature | TJ | | | 150 | °C | | 2 |
| Operating Ambient Temperature Range | TA | -55 | 25 | 125 | °C | | 2 |
| Output Current High | IOH | | | -24 | mA | | 2 |
| Output Current Low | IOL | | | 24 | mA | | 2 |
| Minimum High Level Input Voltage, VCC 3.0 V | VIH | 2.1 | 1.5 | | V | VCC = 3.0 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 |
| Minimum High Level Input Voltage, VCC 4.5 V | VIH | 3.15 | 2.25 | | V | VCC = 4.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 |
| Minimum High Level Input Voltage, VCC 5.5 V | VIH | 3.85 | 2.75 | | V | VCC = 5.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 |
| Maximum Low Level Input Voltage, VCC 3.0 V | VIL | | 1.5 | 0.9 | V | VCC = 3.0 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 |
| Maximum Low Level Input Voltage, VCC 4.5 V | VIL | | 2.25 | 1.35 | V | VCC = 4.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 |
| Maximum Low Level Input Voltage, VCC 5.5 V | VIL | | 2.75 | 1.65 | V | VCC = 5.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA = −55 °C to +125 °C | 3 |
| Minimum High Level Output Voltage, VCC 3.0 V | VOH | 2.9 | 2.99 | | V | VCC = 3.0 V; IOUT = −50 µA; TA = −55 °C to +125 °C | 3 |
| Minimum High Level Output Voltage, VCC 4.5 V | VOH | 4.4 | 4.49 | | V | VCC = 4.5 V; IOUT = −50 µA; TA = −55 °C to +125 °C | 3 |
| Minimum High Level Output Voltage, VCC 5.5 V | VOH | 5.4 | 5.49 | | V | VCC = 5.5 V; IOUT = −50 µA; TA = −55 °C to +125 °C | 3 |
| Minimum High Level Output Voltage, VCC 3.0 V, IOH −12 mA | VOH | 2.4 | 2.56 | | V | *VIN = VIL or VIH; IOH = −12 mA; TA = −55 °C to +125 °C | 3 |
| Minimum High Level Output Voltage, VCC 4.5 V, IOH −24 mA | VOH | 3.7 | 3.86 | | V | *VIN = VIL or VIH; IOH = −24 mA; TA = −55 °C to +125 °C | 3 |
| Minimum High Level Output Voltage, VCC 5.5 V, IOH −24 mA | VOH | 4.7 | 4.86 | | V | *VIN = VIL or VIH; IOH = −24 mA; TA = −55 °C to +125 °C | 3 |
| Maximum Low Level Output Voltage, VCC 3.0 V | VOL | | 0.002 | 0.1 | V | VCC = 3.0 V; IOUT = 50 µA; TA = −55 °C to +125 °C | 3 |
| Maximum Low Level Output Voltage, VCC 4.5 V | VOL | | 0.001 | 0.1 | V | VCC = 4.5 V; IOUT = 50 µA; TA = −55 °C to +125 °C | 3 |
| Maximum Low Level Output Voltage, VCC 5.5 V | VOL | | 0.001 | 0.1 | V | VCC = 5.5 V; IOUT = 50 µA; TA = −55 °C to +125 °C | 3 |
| Maximum Low Level Output Voltage, VCC 3.0 V, IOL 12 mA | VOL | | 0.36 | 0.5 | V | *VIN = VIL or VIH; IOL = 12 mA; TA = −55 °C to +125 °C | 3 |
| Maximum Low Level Output Voltage, VCC 4.5 V, IOL 24 mA | VOL | | 0.36 | 0.5 | V | *VIN = VIL or VIH; IOL = 24 mA; TA = −55 °C to +125 °C | 3 |
| Maximum Low Level Output Voltage, VCC 5.5 V, IOL 24 mA | VOL | | 0.36 | 0.5 | V | *VIN = VIL or VIH; IOL = 24 mA; TA = −55 °C to +125 °C | 3 |
| Maximum Input Leakage Current | IIN | | 0.1 | 1 | µA | VCC = 5.5 V; VI = VCC, GND; TA = −55 °C to +125 °C | 3 |
| Minimum Dynamic Output Current (sink) | IOLD | 50 | | | mA | VCC = 5.5 V; VOLD = 1.65 V Max; one output loaded at a time, max 2.0 ms | 3 |
| Minimum Dynamic Output Current (source) | IOHD | -50 | | | mA | VCC = 5.5 V; VOHD = 3.85 V Min; one output loaded at a time, max 2.0 ms | 3 |
| Maximum Quiescent Supply Current | ICC | | 4 | 40 | µA | VCC = 5.5 V; VIN = VCC or GND; TA = −55 °C to +125 °C | 3 |
| Propagation Delay tPLH, VCC 3.3 V | tPLH | 1 | 7 | 11 | ns | VCC = 3.3 V; CL = 50 pF; tr = tf = 3.0 ns; TA = −55 °C to +125 °C | 3 |
| Propagation Delay tPLH, VCC 5.0 V | tPLH | 1 | 6 | 8.5 | ns | VCC = 5.0 V; CL = 50 pF; tr = tf = 3.0 ns; TA = −55 °C to +125 °C | 3 |
| Propagation Delay tPHL, VCC 3.3 V | tPHL | 1 | 5.5 | 9 | ns | VCC = 3.3 V; CL = 50 pF; tr = tf = 3.0 ns; TA = −55 °C to +125 °C | 3 |
| Propagation Delay tPHL, VCC 5.0 V | tPHL | 1 | 4.5 | 7 | ns | VCC = 5.0 V; CL = 50 pF; tr = tf = 3.0 ns; TA = −55 °C to +125 °C | 3 |
## CAD (KiCad official)
- Symbol: `MC74AC00DTR2G`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `mc74ac00dtr2g-etched.step` / `mc74ac00dtr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74ac00dtr2g.step` / `mc74ac00dtr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588876916509696000) (9 pp, sha256 `3de93c5e45a21247`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74ac00dtr2g-datasheet.pdf)