component
MC34063DRG
Public Made by Adomby adom
HANSCHIP semiconductor DC-DC Converters, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC34063DRG
HANSCHIP semiconductor · DC-DC Converters · SOP-8
MC34063DRG from HANSCHIP semiconductor, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Switch Collector | output | Internal switch transistor collector, rated for 40 V collector voltage and up to 1.2 A switch current. |
| 2 | Switch Emitter | passive | Internal switch transistor emitter, rated at 40 V maximum at pin 1 = 40 V. |
| 3 | Timing Capacitor | passive | Timing capacitor connection that sets the switching frequency (up to 180 kHz with CT = 100 pF; datasheet test condition uses CT = 1 nF). |
| 4 | GND | power_in | Ground pin for all internal circuits. |
| 5 | Comparator Inverting Input | input | Inverting input of the internal comparator; comparator input voltage range is -0.3 V to 40 V, with the output voltage set by the divider on this pin against the 1.25 V internal reference. |
| 6 | VCC | power_in | Supply voltage pin, operating from 3 V to 40 V (absolute maximum 40 V). |
| 7 | IPK Sense | input | Peak current sense input that monitors the voltage drop across an external sense resistor Rcs to limit switch peak current (current limit sense voltage 250 to 350 mV; Rcs of 0.2 Ω or more is specified). |
| 8 | Driver Collector | passive | Driver collector voltage pin, rated at 40 V with driver collector current limited to 100 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Frequency (FOSC) | FOSC | 30 | 38 | 45 | kHz | Vpin5 = 0V; TA = 25°C; CT = 1 nF | 5 |
| Charge Current | ICHG | 30 | 38 | 45 | µA | VCC = 5.0V to 40V; TA = 25°C | 5 |
| Discharge Current | IDISCHG | 180 | 240 | 290 | µA | VCC = 5.0V to 40V; TA = 25°C | 5 |
| Discharge to Charge Current Ratio | IDISCHG/ICHG | 5.2 | 6.5 | 7.5 | - | Pin 7 to VCC; TA = 25°C | 5 |
| Current Limit Sense Voltage | VIPK(SENCE) | 250 | 300 | 350 | mV | ICHG = IDISCHG; TA = 25°C | 5 |
| Saturation Voltage, Darlington connection | VCE(SAT) | 1 | 1.3 | V | ISW = 0.8A; Pins 1,8 connected | 5 | |
| Saturation Voltage (see NOTE 4) | VCE(SAT) | 0.45 | 0.8 | V | ISW = 0.8 A; Rpin 8 = 82 to VCC; Forced β = 20 | 5 | |
| DC Current Gain | hFE | 50 | 75 | - | ISW = 0.8 A; VCE = 5.0V; TA = 25°C | 5 | |
| Collector Off-State Current | IC(OFF) | 0.01 | 100 | µA | VCE = 40 V | 5 | |
| Threshold Voltage (25°C) | VTH | 1.225 | 1.25 | 1.275 | V | TA = 25°C | 5 |
| Threshold Voltage (full temperature range) | VTH | 1.21 | 1.29 | V | TA = -40°C to +85°C | 5 | |
| Threshold Voltage Line Regulation | REGLINE | 1.4 | 5 | mV | VCC = 3V to 40V | 5 | |
| Input Bias Current | IIB | -20 | -400 | nA | VIN = 0V | 5 | |
| Supply Current | ICC | 4 | mA | VCC = 5.0V to 40V; CT = 1.0 nF; Pin 7 = VCC; Vpin 5 > Vth; Pin 2 = GND; other pins open | 5 | ||
| Supply Voltage (recommended) | VCC | 3 | 40 | V | 4 | ||
| Ambient Temperature (recommended) | TA | -40 | 85 | °C | 4 | ||
| Power Supply Voltage | VCC | 40 | V | 4 | |||
| Comparator Input Voltage Range | VIR | -0.3 | 40 | V | 4 | ||
| Switch Collector Voltage | VC (SWITCH) | 40 | V | 4 | |||
| Switch Emitter Voltage | VE (SWITCH) | 40 | V | Vpin1 = 40V | 4 | ||
| Switch Collector to Emitter Voltage | VCE (SWITCH) | 40 | V | 4 | |||
| Driver Collector Voltage | VC (DRIVER) | 40 | V | 4 | |||
| Driver Collector Current | IC (DRIVER) | 100 | mA | NOTE 2 | 4 | ||
| Switch Current | ISW | 1.2 | A | 4 | |||
| Operating Junction Temperature | TJ | 150 | °C | 4 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 4 | ||
| ESD for MC34063 | 3000 | V | 4 | ||||
| Lead Temperature (Soldering, 10 seconds) | TL | 245 | °C | 10 seconds | 4 | ||
| Power Dissipation (SOP) | PD | 625 | mW | TA = 25°C | 4 | ||
| Thermal Resistance (SOP) | RθJA | 160 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
MC34063DRG - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
mc34063drg-etched.step/mc34063drg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc34063drg.step/mc34063drg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HANSCHIP semiconductor datasheet (12 pp, sha256
6fccd876cca44e2a, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).