component
MC33FS6510LAE
Public Made by Adomby adom
NXP Semicon Power Management Specialized - PMIC, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MC33FS6510LAE
NXP Semicon · Power Management Specialized - PMIC · LQFP-48(7x7)
MC33FS6510LAE from NXP Semicon, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSUP1 | power_in | Power supply of the device; an external reverse battery protection diode in series is mandatory. |
| 2 | VSUP2 | power_in | Second power supply protected by the external reverse battery protection diode used for VSUP1; VSUP1 and VSUP2 must be connected together externally. |
| 3 | VSENSE | input | Battery voltage sense, must be connected before the reverse battery protection diode with an external series resistor; rated -14 V to 40 V DC. |
| 4 | VSUP3 | power_in | Third power supply dedicated to the device supply, protected by the external reverse battery protection diode and connected between the diode and the input PI filter. |
| 5 | LIN | bidirectional | LIN single-wire bus transmitter and receiver; LIN and FS1B are exclusive, and this LIN part does not use pin 5 as FS1B. |
| 6 | GND_COM | power_in | Dedicated ground for the physical layers (CAN and LIN). |
| 7 | CAN_5V | power_out | Output voltage for the embedded CAN FD interface; DC voltage rated -0.3 V to 8 V. |
| 8 | CANH | bidirectional | CAN output high; must be left open if the CAN function is not used. CAN bus voltage rated -27 V to 40 V. |
| 9 | CANL | bidirectional | CAN output low; must be left open if the CAN function is not used. CAN bus voltage rated -27 V to 40 V. |
| 10 | IO_4 | bidirectional | Digital input (load dump proof) with selectable wake-up or logic-level low-side NMOS gate driver output controlled by SPI; DC rating -0.3 V to 40 V with external series resistor. |
| 11 | IO_5/VKAM | bidirectional | Digital input with wake-up capability or analog supply output providing keep-alive memory supply in low-power mode; IO_5 rated -0.3 V to 20 V and VKAM rated -0.3 V to 8 V. |
| 12 | IO_0 | input | Analog or digital input (load dump proof) with selectable wake-up capability; DC rating -0.3 V to 40 V with external series resistor. |
| 13 | FCRBM | input | Feedback core resistor bridge monitoring input for the midpoint of a redundant VCORE resistor bridge; if unused it must be connected directly to FB_CORE, rated -0.3 V to 8 V. |
| 14 | FS0B | output | Primary fail-safe output, active low, asserted at start-up and on fault detection; open drain, rated -0.3 V to 40 V with external series resistor. |
| 15 | DEBUG | input | Debug mode entry input; DC rating -0.3 V to 40 V. |
| 16 | AGND | power_in | Analog ground connection. |
| 17 | MUX_OUT | output | Multiplexed analog output to be connected to an MCU ADC, with the measured parameter selected through SPI; rated -0.3 V to 8 V. |
| 18 | IO_2 | input | Logic-level digital input with selectable wake-up, used to monitor FCCU error signals from the MCU; rated -0.3 V to 8 V. |
| 19 | IO_3 | input | Logic-level digital input with selectable wake-up, used to monitor FCCU error signals from the MCU; rated -0.3 V to 8 V. |
| 20 | TXD | input | CAN transceiver input from the MCU controlling the CAN bus state, with internal pull-up to VDDIO; leave open if CAN is not used. |
| 21 | RXD | output | CAN receiver output reporting the CAN bus state to the MCU; leave open if CAN is not used. |
| 22 | TXDL | input | LIN transceiver input from the MCU controlling the LIN bus state, with internal pull-up to VDDIO; leave open if LIN is not used. |
| 23 | RXDL | output | LIN receiver output reporting the LIN bus state to the MCU; leave open if LIN is not used. |
| 24 | RSTB | output | Active-low reset output asserted when the safety block reports a failure to reset the MCU; open drain, rated -0.3 V to 8 V and requires external pull-up to VDDIO. |
| 25 | MISO | output | SPI bus primary input / secondary output; output buffer supplied from VDDIO. |
| 26 | MOSI | input | SPI bus primary output / secondary input; rated -0.3 V to 8 V. |
| 27 | SCLK | input | SPI serial clock input; rated -0.3 V to 8 V. |
| 28 | NCS | input | SPI not chip select input, active low; rated -0.3 V to 8 V. |
| 29 | INTB | output | Interrupt output generating a low pulse of configurable duration on an interrupt condition; internal pull-up to VDDIO. |
| 30 | VDDIO | power_in | Input voltage for the MISO output buffer, allowing voltage compatibility with MCU I/Os; rated -0.3 V to 8 V. |
| 31 | SELECT | input | Hardware selection pin for VCCA and VAUX output voltages via an external resistor to GND or VPRE; rated -0.3 V to 8 V. |
| 32 | FB_CORE | input | VCORE voltage feedback, input of the error amplifier; rated -0.3 V to 2.5 V. |
| 33 | COMP_CORE | output | Compensation network output of the VCORE error amplifier; rated -0.3 V to 2.5 V. |
| 34 | VCORE_SNS | input | VCORE output voltage sense input; rated 0.0 V to 8 V. |
| 35 | SW_CORE | output | VCORE output switching point for the FS6500 series; rated -1.0 V to 8 V. |
| 36 | BOOT_CORE | bidirectional | Bootstrap capacitor connection for the VCORE internal NMOS gate drive; rated 0.0 V to 15 V. |
| 37 | VPRE | input | VPRE input voltage sense; rated -0.3 V to 8 V. |
| 38 | VAUX | power_out | VAUX output voltage (5.0 V or 3.3 V selectable) via an external PNP ballast transistor collector connection; rated -2.0 V to 40 V. |
| 39 | VAUX_B | output | VAUX voltage regulator drive; base connection of the external PNP ballast transistor; rated -0.3 V to 40 V. |
| 40 | VAUX_E | output | VAUX voltage regulator drive; emitter connection of the external PNP ballast transistor; rated -0.3 V to 40 V. |
| 41 | VCCA_E | output | VCCA voltage regulator drive; emitter connection of the external PNP ballast transistor; rated -0.3 V to 8 V. |
| 42 | VCCA_B | output | VCCA voltage regulator drive; base connection of the external PNP ballast transistor; rated -0.3 V to 8 V. |
| 43 | VCCA | power_out | VCCA output voltage (5.0 V or 3.3 V selectable) via the collector connection of an external PNP ballast transistor; rated -0.3 V to 8 V. |
| 44 | GATE_LS | output | Low-side MOSFET gate drive for non-inverting buck-boost configuration; rated -0.3 V to 8 V. |
| 45 | DGND | power_in | Digital ground connection. |
| 46 | BOOT_PRE | bidirectional | Bootstrap capacitor connection for the VPRE internal NMOS gate drive; rated -1.0 V to 50 V. |
| 47 | SW_PRE2 | output | Second pre-regulator output switching point; rated -1.0 V to 40 V. |
| 48 | SW_PRE1 | output | First pre-regulator output switching point; rated -1.0 V to 40 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NXP Semicon |
| Package | LQFP-48(7x7) |
| Category | Power Management ICs |
| Pins | 48 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply current in normal mode | ISUP123 | 15 | mA | 17 | |||
| Power supply current for VSUP3 in normal mode | ISUP3 | 3.5 | 5 | mA | 17 | ||
| Power supply current in LPOFF (VSUP = 18 V at TA = 80 °C) | ISUP_LPOFF2 | 42 | 60 | µA | VSUP = 18 V at TA = 80 °C | 17 | |
| Power supply undervoltage warning | VSNS_UV | 7 | 8 | 9 | V | 17 | |
| Power supply undervoltage lockout (power up) | VSUP_UV_7 | 7 | 8 | V | 17 | ||
| Power supply undervoltage lockout (falling, boost configuration) | VSUP_UV_L | 2.7 | V | falling, boost configuration | 17 | ||
| Power supply undervoltage lockout (falling, buck configuration) | VSUP_UV_L_B | 4.5 | V | falling, buck configuration | 17 | ||
| Power supply undervoltage lockout in LPOFF | VSUP_UV_LPOFF | 4.5 | V | 17 | |||
| IPFF input voltage detection | VSUP_IPFF | 21 | 27 | V | 17 | ||
| VPRE output voltage (buck mode) | VPRE | 6.25 | 6.75 | V | Buck mode (VSUP > VSUP_UV_7) | 17 | |
| VPRE output voltage (boost mode) | VPRE | 6 | 7 | V | Boost mode (VSUP ≥ 2.7 V) | 17 | |
| VPRE maximum output current capability | IPRE | 2 | A | Buck or boost with VSUP > VSUP_UV_7 | 17 | ||
| SW_PRE output current limitation in buck-boost mode | IPRE_LIM1 | 3.5 | A | buck-boost mode (VSUP ≤ 28 V) | 17 | ||
| SW_PRE output current limitation in buck mode | IPRE_LIM2 | 2.5 | A | buck mode (VSUP ≤ 28 V) | 17 | ||
| SW_PRE overcurrent detection threshold in buck mode | IPRE_OC | 4.5 | A | buck mode (VSUP ≤ 28 V) | 17 | ||
| VPRE undervoltage detection threshold (falling) | VPRE_UV | 5.5 | 6 | V | 17 | ||
| VPRE shut-off threshold (falling, buck and buck/boost) | VPRE_UV_4P3 | 4.1 | 4.5 | V | falling, buck and buck/boost | 17 | |
| VPRE pass transistor on resistance | RDSON_PRE | 200 | mΩ | VSUP ≤ 28 V | 18 | ||
| VPRE thermal shutdown threshold | TSD_PRE | 160 | °C | 18 | |||
| VCORE feedback input voltage | VCORE_FB | 0.784 | 0.8 | 0.816 | V | 18 | |
| VCORE internal pull-down current | IPD_CORE | 5 | 12 | 25 | mA | active when VCORE is enabled | 18 |
| VCORE output current capability in normal mode | ICORE | 1.5 | A | FS651x | 18 | ||
| VCORE output current limitation | ICORE_LIM | 1.8 | 2.8 | A | FS651x | 18 | |
| VCORE pass transistor on resistance | RDSON_CORE | 200 | mΩ | 18 | |||
| VCORE transient load regulation, 3.3 V range | FS65_LORVCORE_3.3 | -100 | 100 | mV | COUT_VCORE = 40 µF, ICORE = 10 mA to 1.5 A, dICORE/dt ≤ 2.0 A/µs | 19 | |
| VCORE thermal shutdown threshold | TSD_CORE | 160 | °C | 19 | |||
| VCCA output voltage | VCCA | 4.95 | 5 | 5.05 | V | 5.0 V configuration with internal ballast at 100 mA | 19 |
| VCCA output voltage | VCCA | 4.9 | 5 | 5.1 | V | 5.0 V configuration with external ballast at 200 mA | 19 |
| VCCA output voltage | VCCA | 4.85 | 5 | 5.15 | V | 5.0 V configuration with external ballast at 300 mA | 19 |
| VCCA output voltage | VCCA | 3.267 | 3.3 | 3.333 | V | 3.3 V configuration with internal ballast at 100 mA | 19 |
| VCCA output voltage | VCCA | 3.234 | 3.3 | 3.366 | V | 3.3 V configuration with external ballast at 200 mA | 19 |
| VCCA output voltage | VCCA | 3.201 | 3.3 | 3.399 | V | 3.3 V configuration with external ballast at 300 mA | 19 |
| VCCA output current (int. MOSFET) | ICCA_IN | 100 | mA | int. MOSFET | 19 | ||
| VCCA output current (external PNP) | ICCA_OUT | 300 | mA | external PNP | 19 | ||
| VCCA output current limitation (int. MOSFET) | ICCA_LIM_INT | 100 | 675 | mA | int. MOSFET | 19 | |
| VCCA output current limitation (external PNP) | ICCA_LIM_OUT | 300 | 675 | mA | external PNP | 19 | |
| VCCA output voltage foldback threshold | VCCA_LIM_FB | 0.6 | 1.2 | V | 19 | ||
| VCCA thermal shutdown threshold | TSDCCA | 160 | °C | int. MOSFET only | 19 | ||
| VAUX output voltage (5.0 V configuration) | VAUX_5 | 4.85 | 5 | 5.15 | V | 5.0 V configuration | 19 |
| VAUX output voltage (3.3 V configuration) | VAUX_33 | 3.2 | 3.3 | 3.4 | V | 3.3 V configuration | 19 |
| VAUX output current | IAUX_OUT | 400 | mA | 19 | |||
| VAUX output current limitation | IAUX_LIM | 400 | 800 | mA | 20 | ||
| VCAN output voltage | VCAN | 4.8 | 5 | 5.2 | V | VSUP > 6.0 V in buck mode; VSUP > VSUP_UV_L in boost mode | 20 |
| VCAN output current | ICAN_OUT | 100 | mA | 20 | |||
| VCAN undervoltage detection threshold | VCAN_UV | 4.25 | 4.8 | V | 20 | ||
| VCAN overvoltage detection threshold (rising) | VCAN_OV | 5.2 | 5.85 | V | 20 | ||
| VKAM output voltage | VKAM | 3 | 3.5 | 4 | V | 20 | |
| VKAM output current | IKAM_OUT | 3 | mA | 20 | |||
| VKAM output current limitation | IKAM_LIM | 4 | 10 | mA | 20 | ||
| VPRE overvoltage detection threshold | VPRE_OV | 7.2 | 8 | V | 20 | ||
| VCORE FB undervoltage detection threshold | VCORE_FB_UV | 0.67 | 0.773 | V | 20 | ||
| Reset low output level | VRSTB_OL | 0.5 | V | I_RSTB = 2.0 mA | 21 | ||
| Ambient temperature | TA | -40 | 125 | °C | 16 | ||
| Junction temperature | TJ | -40 | 150 | °C | 16 | ||
| Storage temperature | TSTG | -55 | 150 | °C | 16 | ||
| Thermal resistance junction to ambient | RθJA | 30 | °C/W | Per JEDEC JESD51-6 with board (JESD51-7) horizontal | 16 | ||
| Thermal resistance junction to case top | RθJCTOP | 23.8 | °C/W | cold plate method (MIL SPEC - 883 Method 1012.1) | 16 | ||
| Thermal resistance junction to case bottom | RθJCBOTTOM | 0.9 | °C/W | based on simulation without any interface resistance | 16 |
CAD (KiCad official)
- Symbol:
MC33FS6510LAE - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
mc33fs6510lae-etched.step/mc33fs6510lae-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc33fs6510lae.step/mc33fs6510lae.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NXP Semicon datasheet (161 pp, sha256
39f5c318b818b984, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).