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MC33FS6503CAE

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NXP Semicon Power Management Specialized - PMIC, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC33FS6503CAE

NXP Semicon · Power Management Specialized - PMIC · LQFP-48(7x7)

MC33FS6503CAE from NXP Semicon, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSUP1 power_in Power supply of the device, requiring an external reverse battery protection diode in series; rated -1.0 to 40 V.
2 VSUP2 power_in Second power supply protected by the same reverse battery diode as VSUP1 and must be connected externally to VSUP1; rated -1.0 to 40 V.
3 VSENSE input Battery voltage sensing input connected before the reverse battery protection diode through a mandatory series resistor; rated -14 to 40 V.
4 VSUP3 power_in Third device supply, connected between the reverse protection diode and the input PI filter; rated -1.0 to 40 V.
5 FS1B output Second active-low safety output, open drain, asserted low at start-up and on fault with configurable delay or duration versus FS0B; leave open if unused.
6 GND_COM power_in Dedicated ground for the physical layers (CAN).
7 CAN_5V power_out Output voltage of the regulator supplying the embedded CAN FD interface.
8 CANH bidirectional CAN bus high line; leave open if the CAN function is not used.
9 CANL bidirectional CAN bus low line; leave open if the CAN function is not used.
10 IO_4 bidirectional Digital input with wake-up capability (edge or level, load dump proof) or low-side logic-level NMOS gate driver output controlled by SPI.
11 IO_5/VKAM bidirectional Analog or digital input with selectable wake-up capability, or keep-alive memory supply output in low-power mode.
12 IO_0 input Analog or digital input (load dump proof) with selectable wake-up capability, readable via MUX_OUT or SPI; usually the key on/off signal.
13 FCRBM input Feedback core resistor bridge monitoring input for the midpoint of a redundant VCORE resistor bridge; connect directly to FB_CORE if not used.
14 FS0B output First active-low safety output, open drain, asserted low at start-up and when a fault is detected; external pull-up mandatory.
15 DEBUG input Debug mode entry input, sampled at start-up; rated -0.3 to 40 V.
16 AGND power_in Analog ground connection.
17 MUX_OUT output Multiplexed analog output to an MCU ADC, with the parameter selected through SPI.
18 IO_2 input Logic-level digital input with selectable wake-up capability, readable via SPI and usable to monitor MCU FCCU error signals.
19 IO_3 input Logic-level digital input with selectable wake-up capability, readable via SPI and usable to monitor MCU FCCU error signals.
20 TXD input CAN transmit data input from the MCU with internal pull-up to VDDIO; leave open if CAN is not used.
21 RXD output CAN receive data output reporting bus state to the MCU; leave open if CAN is not used.
22 VPU_FS power_out Pull-up output for the FS1B function, internally attached to VPRE through a reverse diode; rated -0.3 to 8 V.
23 n.c. unconnected Not connected in the CAN with FS1B variant (RXDL position of the LIN variant).
24 RSTB bidirectional Active-low open-drain reset output to the MCU, asserted on safety block failure, with reset input monitored to detect external reset; needs pull-up to VDDIO.
25 MISO output SPI data output (secondary output), buffer supplied from VDDIO.
26 MOSI input SPI data input (secondary input).
27 SCLK input SPI serial clock input.
28 NCS input SPI chip select input, active low.
29 INTB output Interrupt output generating a configurable-duration low pulse on interrupt, with internal pull-up to VDDIO.
30 VDDIO power_in Input voltage for the MISO output buffer for MCU I/O voltage compatibility; rated -0.3 to 8 V.
31 SELECT input Hardware selection pin setting VAUX and VCCA output voltages (3.3 V or 5.0 V) via a resistor to ground or VPRE.
32 FB_CORE input VCORE voltage feedback input of the error amplifier; rated -0.3 to 2.5 V.
33 COMP_CORE output Compensation network connection at the VCORE error amplifier output for the FS6500 SMPS.
34 VCORE_SNS input VCORE input voltage sense; rated 0 to 8 V.
35 SW_CORE output VCORE switching output point of the FS6500 step-down converter.
36 BOOT_CORE passive Bootstrap capacitor connection for the VCORE internal NMOS gate drive; rated 0 to 15 V.
37 VPRE power_in VPRE input voltage sense and pre-regulator output (typ 6.5 V); rated -0.3 to 8 V.
38 VAUX output VAUX output voltage, collector connection of the external PNP ballast transistor.
39 VAUX_B output VAUX regulator base drive for the external PNP ballast transistor.
40 VAUX_E output VAUX regulator emitter connection of the external PNP ballast transistor.
41 VCCA_E output VCCA regulator emitter connection of the external PNP ballast transistor.
42 VCCA_B output VCCA regulator base drive for the external PNP ballast transistor.
43 VCCA power_in VCCA output voltage (5.0 V or 3.3 V selectable), collector connection of the external PNP ballast transistor.
44 GATE_LS output Low-side MOSFET gate drive for non-inverting buck-boost configuration; connect to PGND for standard buck.
45 DGND power_in Digital ground connection.
46 BOOT_PRE passive Bootstrap capacitor connection for the VPRE internal NMOS gate drive; rated -1.0 to 50 V.
47 SW_PRE2 output Second pre-regulator output switching point; rated -1.0 to 40 V.
48 SW_PRE1 output First pre-regulator output switching point; rated -1.0 to 40 V.

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package LQFP-48(7x7)
Category Power Management ICs
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature TA -40 125 °C 16
Junction temperature TJ -40 150 °C 16
Storage temperature TSTG -55 150 °C 16
Thermal resistance junction to ambient RθJA 30 °C/W JESD51-6, board JESD51-7 horizontal 16
Thermal resistance junction to case top RθJCTOP 23.8 °C/W 16
Thermal resistance junction to case bottom RθJCBOTTOM 0.9 °C/W 16
Power supply current in normal mode ISUP123 15 mA 17
Power supply current for VSUP3 in normal mode ISUP3 3.5 5 mA 17
Supply current in LPOFF ISUP_LPOFF1 32 µA VSUP = 14 V at TA = 25 °C 17
Supply current in LPOFF ISUP_LPOFF2 42 60 µA VSUP = 18 V at TA = 80 °C 17
Power supply undervoltage warning VSNS_UV 7 8 9 V 17
IPFF input voltage detection VSUP_IPFF 21 27 V 17
Power supply undervoltage lockout (power up) VSUP_UV_7 7 8 V 17
Power supply undervoltage lockout (power up) VSUP_UV_5 5.6 V 17
Power supply undervoltage lockout falling, boost VSUP_UV_L 2.7 V 17
VPRE output voltage, buck mode VPRE 6.25 6.75 V Buck mode (VSUP > VSUP_UV_7) 17
VPRE output voltage, boost mode VPRE 6 7 V Boost mode (VSUP ≥ 2.7 V) 17
VPRE max output current, buck or boost IPRE 2 A Buck or boost with VSUP > VSUP_UV_7 17
SW_PRE current limitation buck-boost IPRE_LIM1 3.5 A VSUP ≤ 28 V 17
SW_PRE current limitation buck IPRE_LIM2 2.5 A VSUP ≤ 28 V 17
VPRE undervoltage detection threshold VPRE_UV 5.5 6 V falling 17
VPRE pass transistor on resistance RDSON_PRE 200 mΩ VSUP ≤ 28 V 18
VCORE feedback input voltage VCORE_FB 0.784 0.8 0.816 V 18
VCORE output current capability, FS650x ICORE 0.8 A normal mode, FS650x 18
VCORE output current limitation, FS650x ICORE_LIM 1 2 A FS650x 18
VCORE pass transistor on resistance RDSON_CORE 200 mΩ 18
VCCA output voltage 5.0 V config VCCA 4.95 5 5.05 V 5.0 V configuration with internal ballast at 100 mA 19
VCCA output voltage 3.3 V config VCCA 3.267 3.3 3.333 V 3.3 V configuration with internal ballast at 100 mA 19
VAUX output voltage 5.0 V VAUX_5 4.85 5 5.15 V 5.0 V configuration 19
VAUX output voltage 3.3 V VAUX_33 3.2 3.3 3.4 V 3.3 V configuration 19
VAUX output current IAUX_OUT 400 mA 19
VCAN output voltage VCAN 4.8 5 5.2 V VSUP > 6.0 V in buck mode; VSUP > VSUP_UV_L in boost mode 20
VKAM output voltage VKAM 3 3.5 4 V 20
Digital supply voltage for MISO output buffer VDDIO 3 5.5 V 23
Reset delay time after power-on reset or from LPOFF tRSTB_POR 12.5 16.5 24.3 ms 26
SPI operation frequency fSPI 0.5 8 MHz 50 % DC 26
VPRE switching frequency fSW_PRE 412 437.5 463 kHz 27
VCORE switching frequency fSW_CORE 2.2 2.34 2.48 MHz 27
Minimum capacitor on VSUP CSUP 47 µF 27
Long duration timer oscillator CLKLDT 31129 32768 34407 Hz 28
Propagation loop delay TXD to RXD tLOOP 255 ns RLOAD = 120 Ω, C between CANH and CANL = 100 pF, C at RXD < 15 pF 29

CAD (KiCad official)

  • Symbol: MC33FS6503CAE
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: mc33fs6503cae-etched.step / mc33fs6503cae-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc33fs6503cae.step / mc33fs6503cae.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (161 pp, sha256 39f5c318b818b984, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF