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MC33972ATEWR2

Public Made by Adom

by adom

NXP Semicon Interface - Specialized, SOIC-32-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MC33972ATEWR2

NXP Semicon · Interface - Specialized · SOIC-32-300mil

MC33972ATEWR2 from NXP Semicon, in a SOIC-32-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground for logic, analog, and switch to battery inputs.
2 SI input SPI control data input from the MCU to the 33972, latched on the falling edge of SCLK.
3 SCLK input SPI control clock input that must be held logic LOW whenever CS makes any transition.
4 CS input SPI chip select input from the MCU; logic LOW allows data to be transferred in.
5 SP0 input Programmable switch-to-battery or switch-to-ground input compared with a 4.0 V reference.
6 SP1 input Programmable switch-to-battery or switch-to-ground input compared with a 4.0 V reference.
7 SP2 input Programmable switch-to-battery or switch-to-ground input compared with a 4.0 V reference.
8 SP3 input Programmable switch-to-battery or switch-to-ground input compared with a 4.0 V reference.
9 SG0 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
10 SG1 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
11 SG2 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
12 SG3 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
13 SG4 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
14 SG5 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
15 SG6 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
16 VPWR power_in Battery supply input that requires external reverse battery protection; maximum input voltage is 50 V.
17 WAKE bidirectional Open-drain wake-up output designed to control a power supply enable pin.
18 SG13 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
19 SG12 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
20 SG11 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
21 SG10 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
22 SG9 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
23 SG8 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
24 SG7 input Switch-to-ground input compared with a 4.0 V reference; voltages less than 4.0 V are considered closed.
25 SP4 input Programmable switch-to-battery or switch-to-ground input compared with a 4.0 V reference.
26 SP5 input Programmable switch-to-battery or switch-to-ground input compared with a 4.0 V reference.
27 SP6 input Programmable switch-to-battery or switch-to-ground input compared with a 4.0 V reference.
28 SP7 input Programmable switch-to-battery or switch-to-ground input compared with a 4.0 V reference.
29 INT bidirectional Open-drain output to the MCU used to indicate an input switch change of state.
30 AMUX output Analog multiplex output that provides the buffered analog switch input for the MCU to read.
31 VDD power_in 3.3/5.0 V supply that sets the SPI communication level for the SO driver.
32 SO output SPI slave out providing digital switch status data from the 33972 to the MCU.

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package SOIC-32-300mil
Category Interface ICs
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (CS, SI, SO, SCLK, INT, AMUX pins) VDD -0.3 7 VDC CS, SI, SO, SCLK, INT, AMUX pins 5
WAKE pin voltage -0.3 40 VDC WAKE pin 5
VPWR Supply Voltage VPWR -0.3 50 VDC 5
VPWR Supply Voltage at -40 C VPWR -0.3 45 VDC at -40 C 5
Switch Input Voltage Range -14 40 VDC 5
Frequency of SPI Operation 6 MHz VDD = 5.0 V 5
Operating Temperature Ambient TA -40 125 C 5
Operating Temperature Junction TJ -40 150 C 5
Storage Temperature TSTG -55 150 C 5
Power Dissipation PD 1.7 W TA = 25 C 5
Logic Supply Voltage VDD 3.1 5.25 V 6
Supply Voltage Range Quasi-functional VPWR(QF) 5.5 26 V Quasi-functional 6
Supply Voltage Range Fully Operational VPWR(FO) 8 26 V Fully Operational 6
Supply Current IPWR(ON) 2 4 mA All Switches Open, Normal Mode, Tri-state Disabled 6
Sleep State Supply Current IPWR(SS) 40 70 100 µA Scan Timer = 64 ms, Switches Open 6
Logic Supply Current IDD 0.25 0.5 mA All Switches Open, Normal mode 6
Sleep State Logic Supply Current IDD(SS) 10 20 µA Scan Timer = 64 ms, Switches Open 6
Pulse Wetting Current Switch-to-Battery (Current Sink) IPULSE 12 15 18 mA 6
Pulse Wetting Current Switch-to-Ground (Current Source) IPULSE 12 16 18 mA 6
Sustain Current Switch-to-Battery Input (Current Sink) ISUSTAIN 1.8 2 2.2 mA 6
Sustain Current Switch-to-Ground Input (Current Source) ISUSTAIN 1.8 2 2.2 mA 6
Sustain Current Matching Between Channels on Switch-to-Ground I/Os IMATCH 2 4 % 6
Input Offset Current When Selected as Analog IOFFSET -2 1.4 2 µA 6
Input Offset Voltage When Selected as Analog V(SP&SGINPUTS) to AMUX Output VOFFSET -10 2.5 10 mV 6
Analog Operational Amplifier Output Voltage Sink VOL 10 30 mV Sink 250 µA 6
Switch Detection Threshold VTH 3.7 4 4.3 V 6
Switch Input Voltage Range (33972A) VIN -14 40 V 33972A 6
Temperature Monitor TLIM 155 185 C 6
Temperature Monitor Hysteresis TLIM(HYS) 5 10 15 C 6
Input Logic Voltage Thresholds VINLOGIC 0.8 2.2 V 7
SCLK, SI, Tri-state SO Input Current ISCLK, ISI, ISO(TRI) -10 10 µA 0 V to VDD 7
CS Input Current ICS -10 10 µA CS = VDD 7
CS Pull-up Current ICS 30 100 µA CS = 0 V 7
SO Low-state Output Voltage VSO(LOW) 0.4 V ISO(HIGH) = 1.6mA 7
Input Capacitance on SCLK, SI, Tri-state SO CIN 20 pF 7
INT Internal Pull-up Current 15 40 100 µA 7
INT Voltage (low) VINT(LOW) 0.2 0.4 V IINT = 1.0 mA 7
WAKE Internal Pull-up Current IWAKE(PU) 20 40 100 µA 7
WAKE Voltage (high) VWAKE(HIGH) 4 4.3 5.3 V WAKE = Open Circuit 7
WAKE Voltage (low) VWAKE(LOW) 0.2 0.4 V IWAKE = 1.0 mA 7
WAKE Maximum Voltage Applied Through External Pull-up VWAKE(MAX) 40 V 7
Pulse Wetting Current Time tPULSE(ON) 15 16 20 ms 8
Interrupt Delay Time Normal Mode tINT-DLY 5 16 µs Normal Mode 8
Sleep Mode Switch Scan Time tSCAN 100 200 300 µs Sleep Mode 8
Calibrated Scan Timer Accuracy Sleep Mode tSCAN TIMER 10 % Sleep Mode 8
Calibrated Interrupt Timer Accuracy Sleep Mode tINT TIMER 10 % Sleep Mode 8
Required Low-state Duration on VPWR for Reset tRESET 10 µs VPWR ≤ 0.2 V 8
Falling Edge of CS to Rising Edge of SCLK Required Set-up Time tLEAD 100 ns 8
Falling Edge of SCLK to Rising Edge of CS Required Set-up Time tLAG 50 ns 8
SI to Falling Edge of SCLK Required Set-up Time tSI(SU) 16 ns 8
Falling Edge of SCLK to SI Required Hold Time tSI(HOLD) 20 ns 8
Time from Falling Edge of CS to SO Low-impedance tSO(EN) 55 ns 8
Time from Rising Edge of CS to SO High-impedance tSO(DIS) 55 ns 8
Time from Rising Edge of SCLK to SO Data Valid tVALID 25 55 ns 8
Thermal Resistance Non-Exposed Pad Junction to Ambient RJA 74 C/W Non-Exposed Pad 5
Thermal Resistance Non-Exposed Pad Junction to Lead RJL 25 C/W Non-Exposed Pad 5
Thermal Resistance Exposed Pad Junction to Ambient RJA 71 C/W Exposed Pad 5
Thermal Resistance Exposed Pad Junction to Exposed Pad RJC 1.2 C/W Exposed Pad 5

CAD (KiCad official)

  • Symbol: MC33972ATEWR2
  • Footprint: Package_SO:SOIC-32_7.518x20.777mm_P1.27mm
  • 3D model: SOIC-32-300mil (KiCad packages3D, STEP)
  • 3D model files: mc33972atewr2-etched.step / mc33972atewr2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc33972atewr2.step / mc33972atewr2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (32 pp, sha256 4fb56b14a3ad7a3a, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF