component
MC14541BDR2G
Public Made by Adomby adom
onsemi Timers / Counters, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC14541BDR2G
onsemi · Timers / Counters · SOIC-14
MC14541BDR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Rtc | passive | External resistor for RC oscillator timing network; recommended 56 kΩ with Ctc = 1000 pF per Figure 3. |
| 2 | Ctc | passive | External capacitor for RC oscillator timing network; recommended 1000 pF with Rtc = 56 kΩ per Figure 3. |
| 3 | RS | passive | Series resistor for oscillator biasing; minimum 10 kΩ, recommended ≈ 2 × Rtc per Figure 3. |
| 4 | NC | unconnected | No connection. |
| 5 | AR | input | Automatic reset control input; logic 0 enables automatic power-on reset for supply range 3.0-18 Vdc, logic 1 disables auto reset for 8.5-18 Vdc low-power operation. |
| 6 | MR | input | Master reset input; logic 1 pulse (300-900 ns minimum width depending on VDD) resets all counter stages synchronously independent of automatic reset state. |
| 7 | VSS | power_in | Ground return, negative supply reference (0 Vdc). |
| 8 | Q | output | Programmable timer output; frequency determined by A and B select inputs, output level determined by Q/Q SEL pin, VOL ≤ 0.05 Vdc and VOH ≥ (VDD − 0.05) Vdc. |
| 9 | Q/Q SEL | input | Output level selection input; logic 0 sets Q output low after reset, logic 1 sets Q output high after reset. |
| 10 | MODE | input | Operating mode control input; logic 0 selects single-cycle mode (output changes after 2ⁿ⁻¹ counts and remains unchanged), logic 1 selects recycle mode (output continually toggles). |
| 11 | NC | unconnected | No connection. |
| 12 | A | input | Frequency division select input A; together with pin 13 (B) selects output from 2⁸, 2¹⁰, 2¹³, or 2¹⁶ counter stage per Frequency Selection Table. |
| 13 | B | input | Frequency division select input B; together with pin 12 (A) selects output from 2⁸, 2¹⁰, 2¹³, or 2¹⁶ counter stage per Frequency Selection Table. |
| 14 | VDD | power_in | Positive supply voltage input; operating range 3.0-18 Vdc with automatic reset enabled (pin 5 = 0), or 8.5-18 Vdc with automatic reset disabled (pin 5 = 1); maximum rating +18.0 Vdc. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Clock/Timing |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
MC14541BDR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc14541bdr2g-etched.step/mc14541bdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc14541bdr2g.step/mc14541bdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (9 pp, sha256
f181a4975a73646b, retrieved 2026-09-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).