MC14094BDR2G

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  "type": "component",
  "slug": "mc14094bdr2g",
  "title": "MC14094BDR2G",
  "brief": "onsemi Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
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  "component": {
    "mpn": "MC14094BDR2G",
    "manufacturer": "onsemi",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586194462075211776",
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    },
    "distributor_links": {
      "lcsc": "C161627",
      "mouser": "863-MC14094BDR2G"
    },
    "distributor_check": {
      "checked_at": "2026-10-09T23:03:31Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "deferred",
        "error": "shared DigiKey quota guard: 539 calls left today"
      },
      "mouser": {
        "pn": "863-MC14094BDR2G",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "STROBE",
        "type": "input",
        "description": "Strobe input: data is latched on the negative transition of strobe, and data propagates through the latches while strobe is high."
      },
      {
        "number": "2",
        "name": "DATA",
        "type": "input",
        "description": "Serial data input to shift register stage 1, shifted in on the positive clock transition."
      },
      {
        "number": "3",
        "name": "CLOCK",
        "type": "input",
        "description": "Clock input: data shifts on the positive clock transition, and the Q'S serial output shifts on the following negative transition."
      },
      {
        "number": "4",
        "name": "Q1",
        "type": "tri_state",
        "description": "Parallel 3-state output of data latch 1, placed in high impedance by a logic Low on Output Enable; rated to drive two low-power TTL loads over the rated temperature range."
      },
      {
        "number": "5",
        "name": "Q2",
        "type": "tri_state",
        "description": "Parallel 3-state output of data latch 2, placed in high impedance by a logic Low on Output Enable; rated to drive two low-power TTL loads over the rated temperature range."
      },
      {
        "number": "6",
        "name": "Q3",
        "type": "tri_state",
        "description": "Parallel 3-state output of data latch 3, placed in high impedance by a logic Low on Output Enable; rated to drive two low-power TTL loads over the rated temperature range."
      },
      {
        "number": "7",
        "name": "Q4",
        "type": "tri_state",
        "description": "Parallel 3-state output of data latch 4, placed in high impedance by a logic Low on Output Enable; rated to drive two low-power TTL loads over the rated temperature range."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply and voltage reference for all ratings; inputs and outputs must stay within VSS ≤ (Vin or Vout) ≤ VDD."
      },
      {
        "number": "9",
        "name": "QS",
        "type": "output",
        "description": "High-speed serial output from shift register stage 7, updated on the positive clock transition for cascaded systems."
      },
      {
        "number": "10",
        "name": "Q'S",
        "type": "output",
        "description": "Low-speed serial output from shift register stage 7, shifted on the following negative clock transition for cascaded systems."
      },
      {
        "number": "11",
        "name": "Q8",
        "type": "tri_state",
        "description": "Parallel 3-state output of data latch 8, placed in high impedance by a logic Low on Output Enable; rated to drive two low-power TTL loads over the rated temperature range."
      },
      {
        "number": "12",
        "name": "Q7",
        "type": "tri_state",
        "description": "Parallel 3-state output of data latch 7, placed in high impedance by a logic Low on Output Enable; rated to drive two low-power TTL loads over the rated temperature range."
      },
      {
        "number": "13",
        "name": "Q6",
        "type": "tri_state",
        "description": "Parallel 3-state output of data latch 6, placed in high impedance by a logic Low on Output Enable; rated to drive two low-power TTL loads over the rated temperature range."
      },
      {
        "number": "14",
        "name": "Q5",
        "type": "tri_state",
        "description": "Parallel 3-state output of data latch 5, placed in high impedance by a logic Low on Output Enable; rated to drive two low-power TTL loads over the rated temperature range."
      },
      {
        "number": "15",
        "name": "OUTPUT ENABLE",
        "type": "input",
        "description": "A logic Low forces parallel outputs Q1 through Q8 into the high-impedance state; a logic High enables them."
      },
      {
        "number": "16",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply; the DC supply voltage range is −0.5 V to +18.0 V with respect to VSS (maximum ratings)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The page 2 pin assignment diagram is scrambled in the text extraction, so the pin numbers were recon; VSS=8 and VDD=16 are not labelled as numbers in the extracted text; they follow from the standard 16; The datasheet does not label QS and Q'S as 3-state. The truth table shows them driven as outputs wit",
          "1/16 pin names appear NOWHERE in the datasheet text: [\"10:Q'S@p2\"]"
        ],
        "pages_sent": 9,
        "cost_usd": 0.072,
        "at": "2026-10-09T23:01:40"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586194462075211776",
        "pages": 9,
        "sha256": "356c23430343651d",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-09",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
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        "zmin_mm": -0.0,
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        "sha256": "64e74852752eaf764f0b72b03a1c2b254ae770e3e3595f892d75a92842bc50dc",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "onsemi",
      "Package": "SOIC-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "variants": [],
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  "discovery_pitch": "MC14094BDR2G (onsemi) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
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