component
MC14017BDR2G
Public Made by Adomby adom
onsemi Counters / Dividers, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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mc14017bdr2g: factory component page (tier=mfr)
4 files changed
+54−50
README.md+20−19@@ -8,22 +8,22 @@ MC14017BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted fr | Pin | Name | Type | Function | |---|---|---|---|-| 1 | Q5 | output | Decoded decimal output 5. Active-high; high for one clock period when count = 5. |-| 2 | Q1 | output | Decoded decimal output 1. Active-high; high for one clock period when count = 1. |-| 3 | Q0 | output | Decoded decimal output 0. Active-high; high for one clock period when count = 0. |-| 4 | Q2 | output | Decoded decimal output 2. Active-high; high for one clock period when count = 2. |-| 5 | Q6 | output | Decoded decimal output 6. Active-high; high for one clock period when count = 6. |-| 6 | Q7 | output | Decoded decimal output 7. Active-high; high for one clock period when count = 7. |-| 7 | Q3 | output | Decoded decimal output 3. Active-high; high for one clock period when count = 3. |-| 8 | VSS | power_in | Negative supply / ground reference. |-| 9 | Q8 | output | Decoded decimal output 8. Active-high; high for one clock period when count = 8. |-| 10 | Q4 | output | Decoded decimal output 4. Active-high; high for one clock period when count = 4. |-| 11 | Q9 | output | Decoded decimal output 9. Active-high; high for one clock period when count = 9. |-| 12 | CARRY OUT | output | Carry-out output. Provides one output pulse for every 10 clock input pulses; used to cascade multiple counters. |-| 13 | CLOCK ENABLE | input | Clock enable / inhibit input. When high, clock input is inhibited and counter does not advance. |-| 14 | CLOCK | input | Clock input. Counter advances one count on the positive-going edge when clock enable is low. |-| 15 | RESET | input | Master reset input. Active-high; forces counter to zero (Q0 high) asynchronously. |-| 16 | VDD | power_in | Positive supply voltage. Operating range 3.0 V to 18 V. |+| 1 | Q5 | output | Decoded output Q5. Active-high decimal decode output, high only during the 5th count of the Johnson sequence; otherwise low. CMOS push-pull output; drive typically -1.3 mA source / 1.3 mA sink at VDD=10 V. |+| 2 | Q1 | output | Decoded output Q1. Active-high decimal decode output, high only during the 1st count of the Johnson sequence; otherwise low. CMOS push-pull output. |+| 3 | Q0 | output | Decoded output Q0. Active-high decimal decode output, high only during the 0th count of the Johnson sequence and after RESET; otherwise low. |+| 4 | Q2 | output | Decoded output Q2. Active-high decimal decode output, high only during the 2nd count of the Johnson sequence; otherwise low. |+| 5 | Q6 | output | Decoded output Q6. Active-high decimal decode output, high only during the 6th count of the Johnson sequence; otherwise low. |+| 6 | Q7 | output | Decoded output Q7. Active-high decimal decode output, high only during the 7th count of the Johnson sequence; otherwise low. |+| 7 | Q3 | output | Decoded output Q3. Active-high decimal decode output, high only during the 3rd count of the Johnson sequence; otherwise low. |+| 8 | VSS | power_in | Negative supply / ground reference. Tie to 0 V. All input and output voltages are referenced to VSS. |+| 9 | Q8 | output | Decoded output Q8. Active-high decimal decode output, high only during the 8th count of the Johnson sequence; otherwise low. |+| 10 | Q4 | output | Decoded output Q4. Active-high decimal decode output, high only during the 4th count of the Johnson sequence; otherwise low. |+| 11 | Q9 | output | Decoded output Q9. Active-high decimal decode output, high only during the 9th (last) count of the Johnson sequence; otherwise low. |+| 12 | Cout | output | Carry Out. High while the internal count is 0-4 and low while 5-9, producing one full clock cycle per ten input clocks. Used to cascade multiple MC14017B stages for divide-by-N counting. |+| 13 | CE | input | Clock Enable (active-low, shown overlined as CE). When low the CLOCK input advances the counter on positive edges; when high the counter is inhibited. Can alternatively be used as a negative-edge clock while CLOCK is held low. |+| 14 | CLOCK | input | Clock input. Counter advances on the positive-going edge when CE is low. DC clock input circuit allows unlimited rise/fall times. Max clock frequency 5 MHz at VDD=5 V, 12 MHz at 10 V, 16 MHz at 15 V. |+| 15 | RESET | input | Asynchronous master reset (active-high). When high, forces counter to state 0 (Q0 high, Q1-Q9 low, Cout high). Must be low for normal counting. |+| 16 | VDD | power_in | Positive supply voltage. Operating range 3.0 to 18 Vdc (absolute max -0.5 to +18 V). Bypass locally with a ceramic capacitor to VSS. | ## Key specifications @@ -36,9 +36,10 @@ MC14017BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted fr ## Ordering variants -- `MC14017BDR2GDR2G`-- `MC14017BDR2GDG`-- `MC14017BDR2GCPG`+- `MC14017BDR2GMC14017BDG`+- `MC14017BDR2GNLV14017BDG`+- `MC14017BDR2G`+- `MC14017BDR2GNLV14017BDR2G` ## CAD (KiCad official)
mc14017bdr2g.kicad_sym+2−2@@ -53,11 +53,11 @@ (number "14" (effects (font (size 1.27 1.27)))) ) (pin input line (at 17.78 0.00 180) (length 5.08)- (name "CLOCK ENABLE" (effects (font (size 1.27 1.27))))+ (name "CE" (effects (font (size 1.27 1.27)))) (number "13" (effects (font (size 1.27 1.27)))) ) (pin output line (at 17.78 -2.54 180) (length 5.08)- (name "CARRY OUT" (effects (font (size 1.27 1.27))))+ (name "Cout" (effects (font (size 1.27 1.27)))) (number "12" (effects (font (size 1.27 1.27)))) ) (pin output line (at 17.78 -5.08 180) (length 5.08)
mc14017bdr2g.lbr+13−7@@ -50,7 +50,7 @@ <layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> </layers> <library>-<description></description>+<description>onsemi Counters / Dividers, SOIC-16</description> <packages> <package name="SOIC-16_3.9x9.9mm_P1.27mm"> <description>SOIC-16, 3.9 x 9.9 mm, 1.27 mm pitch</description>@@ -94,6 +94,7 @@ </packages> <symbols> <symbol name="MC14017BDR2G">+ <description>onsemi Counters / Dividers, SOIC-16</description> <wire x1="-12.7" y1="10.16" x2="12.7" y2="10.16" width="0.254" layer="94"/> <wire x1="12.7" y1="10.16" x2="12.7" y2="-12.7" width="0.254" layer="94"/> <wire x1="12.7" y1="-12.7" x2="-12.7" y2="-12.7" width="0.254" layer="94"/>@@ -111,8 +112,8 @@ <pin name="VDD" x="17.78" y="7.62" length="middle" direction="pwr" rot="R180"/> <pin name="RESET" x="17.78" y="5.08" length="middle" direction="in" rot="R180"/> <pin name="CLOCK" x="17.78" y="2.54" length="middle" direction="in" rot="R180"/>- <pin name="CLOCK_ENABLE" x="17.78" y="0" length="middle" direction="in" rot="R180"/>- <pin name="CARRY_OUT" x="17.78" y="-2.54" length="middle" direction="out" rot="R180"/>+ <pin name="CE" x="17.78" y="0" length="middle" direction="in" rot="R180"/>+ <pin name="Cout" x="17.78" y="-2.54" length="middle" direction="out" rot="R180"/> <pin name="Q9" x="17.78" y="-5.08" length="middle" direction="out" rot="R180"/> <pin name="Q4" x="17.78" y="-7.62" length="middle" direction="out" rot="R180"/> <pin name="Q8" x="17.78" y="-10.16" length="middle" direction="out" rot="R180"/>@@ -120,7 +121,7 @@ </symbols> <devicesets> <deviceset name="MC14017BDR2G" prefix="U">- <description></description>+ <description>onsemi Counters / Dividers, SOIC-16</description> <gates> <gate name="G$1" symbol="MC14017BDR2G" x="0" y="0"/> </gates>@@ -138,13 +139,18 @@ <connect gate="G$1" pin="VDD" pad="16"/> <connect gate="G$1" pin="RESET" pad="15"/> <connect gate="G$1" pin="CLOCK" pad="14"/>- <connect gate="G$1" pin="CLOCK_ENABLE" pad="13"/>- <connect gate="G$1" pin="CARRY_OUT" pad="12"/>+ <connect gate="G$1" pin="CE" pad="13"/>+ <connect gate="G$1" pin="Cout" pad="12"/> <connect gate="G$1" pin="Q9" pad="11"/> <connect gate="G$1" pin="Q4" pad="10"/> <connect gate="G$1" pin="Q8" pad="9"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="MC14017BDR2G" constant="no"/>+ <attribute name="MANUFACTURER" value="onsemi" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+19−22@@ -32,97 +32,97 @@ "number": "1", "name": "Q5", "type": "output",- "description": "Decoded decimal output 5. Active-high; high for one clock period when count = 5."+ "description": "Decoded output Q5. Active-high decimal decode output, high only during the 5th count of the Johnson sequence; otherwise low. CMOS push-pull output; drive typically -1.3 mA source / 1.3 mA sink at VDD=10 V." }, { "number": "2", "name": "Q1", "type": "output",- "description": "Decoded decimal output 1. Active-high; high for one clock period when count = 1."+ "description": "Decoded output Q1. Active-high decimal decode output, high only during the 1st count of the Johnson sequence; otherwise low. CMOS push-pull output." }, { "number": "3", "name": "Q0", "type": "output",- "description": "Decoded decimal output 0. Active-high; high for one clock period when count = 0."+ "description": "Decoded output Q0. Active-high decimal decode output, high only during the 0th count of the Johnson sequence and after RESET; otherwise low." }, { "number": "4", "name": "Q2", "type": "output",- "description": "Decoded decimal output 2. Active-high; high for one clock period when count = 2."+ "description": "Decoded output Q2. Active-high decimal decode output, high only during the 2nd count of the Johnson sequence; otherwise low." }, { "number": "5", "name": "Q6", "type": "output",- "description": "Decoded decimal output 6. Active-high; high for one clock period when count = 6."+ "description": "Decoded output Q6. Active-high decimal decode output, high only during the 6th count of the Johnson sequence; otherwise low." }, { "number": "6", "name": "Q7", "type": "output",- "description": "Decoded decimal output 7. Active-high; high for one clock period when count = 7."+ "description": "Decoded output Q7. Active-high decimal decode output, high only during the 7th count of the Johnson sequence; otherwise low." }, { "number": "7", "name": "Q3", "type": "output",- "description": "Decoded decimal output 3. Active-high; high for one clock period when count = 3."+ "description": "Decoded output Q3. Active-high decimal decode output, high only during the 3rd count of the Johnson sequence; otherwise low." }, { "number": "8", "name": "VSS", "type": "power_in",- "description": "Negative supply / ground reference."+ "description": "Negative supply / ground reference. Tie to 0 V. All input and output voltages are referenced to VSS." }, { "number": "9", "name": "Q8", "type": "output",- "description": "Decoded decimal output 8. Active-high; high for one clock period when count = 8."+ "description": "Decoded output Q8. Active-high decimal decode output, high only during the 8th count of the Johnson sequence; otherwise low." }, { "number": "10", "name": "Q4", "type": "output",- "description": "Decoded decimal output 4. Active-high; high for one clock period when count = 4."+ "description": "Decoded output Q4. Active-high decimal decode output, high only during the 4th count of the Johnson sequence; otherwise low." }, { "number": "11", "name": "Q9", "type": "output",- "description": "Decoded decimal output 9. Active-high; high for one clock period when count = 9."+ "description": "Decoded output Q9. Active-high decimal decode output, high only during the 9th (last) count of the Johnson sequence; otherwise low." }, { "number": "12",- "name": "CARRY OUT",+ "name": "Cout", "type": "output",- "description": "Carry-out output. Provides one output pulse for every 10 clock input pulses; used to cascade multiple counters."+ "description": "Carry Out. High while the internal count is 0-4 and low while 5-9, producing one full clock cycle per ten input clocks. Used to cascade multiple MC14017B stages for divide-by-N counting." }, { "number": "13",- "name": "CLOCK ENABLE",+ "name": "CE", "type": "input",- "description": "Clock enable / inhibit input. When high, clock input is inhibited and counter does not advance."+ "description": "Clock Enable (active-low, shown overlined as CE). When low the CLOCK input advances the counter on positive edges; when high the counter is inhibited. Can alternatively be used as a negative-edge clock while CLOCK is held low." }, { "number": "14", "name": "CLOCK", "type": "input",- "description": "Clock input. Counter advances one count on the positive-going edge when clock enable is low."+ "description": "Clock input. Counter advances on the positive-going edge when CE is low. DC clock input circuit allows unlimited rise/fall times. Max clock frequency 5 MHz at VDD=5 V, 12 MHz at 10 V, 16 MHz at 15 V." }, { "number": "15", "name": "RESET", "type": "input",- "description": "Master reset input. Active-high; forces counter to zero (Q0 high) asynchronously."+ "description": "Asynchronous master reset (active-high). When high, forces counter to state 0 (Q0 high, Q1-Q9 low, Cout high). Must be low for normal counting." }, { "number": "16", "name": "VDD", "type": "power_in",- "description": "Positive supply voltage. Operating range 3.0 V to 18 V."+ "description": "Positive supply voltage. Operating range 3.0 to 18 Vdc (absolute max -0.5 to +18 V). Bypass locally with a ceramic capacitor to VSS." } ], "provenance": {@@ -186,8 +186,5 @@ "docs/mc14017bdr2g-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": {- "public": true- }+ ] }