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MC14017BDR2G

Public Made by Adom

by adom

onsemi Counters / Dividers, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MC14017BDR2G

onsemi · Counters / Dividers · SOIC-16

MC14017BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q5 output Decoded output Q5. Active-high decimal decode output, high only during the 5th count of the Johnson sequence; otherwise low. CMOS push-pull output; drive typically -1.3 mA source / 1.3 mA sink at VDD=10 V.
2 Q1 output Decoded output Q1. Active-high decimal decode output, high only during the 1st count of the Johnson sequence; otherwise low. CMOS push-pull output.
3 Q0 output Decoded output Q0. Active-high decimal decode output, high only during the 0th count of the Johnson sequence and after RESET; otherwise low.
4 Q2 output Decoded output Q2. Active-high decimal decode output, high only during the 2nd count of the Johnson sequence; otherwise low.
5 Q6 output Decoded output Q6. Active-high decimal decode output, high only during the 6th count of the Johnson sequence; otherwise low.
6 Q7 output Decoded output Q7. Active-high decimal decode output, high only during the 7th count of the Johnson sequence; otherwise low.
7 Q3 output Decoded output Q3. Active-high decimal decode output, high only during the 3rd count of the Johnson sequence; otherwise low.
8 VSS power_in Negative supply / ground reference. Tie to 0 V. All input and output voltages are referenced to VSS.
9 Q8 output Decoded output Q8. Active-high decimal decode output, high only during the 8th count of the Johnson sequence; otherwise low.
10 Q4 output Decoded output Q4. Active-high decimal decode output, high only during the 4th count of the Johnson sequence; otherwise low.
11 Q9 output Decoded output Q9. Active-high decimal decode output, high only during the 9th (last) count of the Johnson sequence; otherwise low.
12 Cout output Carry Out. High while the internal count is 0-4 and low while 5-9, producing one full clock cycle per ten input clocks. Used to cascade multiple MC14017B stages for divide-by-N counting.
13 CE input Clock Enable (active-low, shown overlined as CE). When low the CLOCK input advances the counter on positive edges; when high the counter is inhibited. Can alternatively be used as a negative-edge clock while CLOCK is held low.
14 CLOCK input Clock input. Counter advances on the positive-going edge when CE is low. DC clock input circuit allows unlimited rise/fall times. Max clock frequency 5 MHz at VDD=5 V, 12 MHz at 10 V, 16 MHz at 15 V.
15 RESET input Asynchronous master reset (active-high). When high, forces counter to state 0 (Q0 high, Q1-Q9 low, Cout high). Must be low for normal counting.
16 VDD power_in Positive supply voltage. Operating range 3.0 to 18 Vdc (absolute max -0.5 to +18 V). Bypass locally with a ceramic capacitor to VSS.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • MC14017BDG
  • MC14017BDR2GNLV14017BDG
  • MC14017BDR2G
  • MC14017BDR2GNLV14017BDR2G

CAD (KiCad official)

  • Symbol: MC14017BDR2G
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: mc14017bdr2g-etched.step / mc14017bdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc14017bdr2g.step / mc14017bdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 cd6005a17166a6cd, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF