component

MC14014BDR2G

Public Made by Adom

by adom

onsemi Shifting Register, SOIC-16. Pinout settled in review by an AI reviewer against the manufacturer's datasheet, KiCad symbol/footprint/3D.

componentlogic icsmc14014bdr2gfactory-2.0.0extractor-text

Verified MC14014BDR2G

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MC14014BDR2G · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 10-page datasheet
  • ✓distributor: lcsc C274655, digikey 488-MC14014BDR2GTR-ND, mouser 863-MC14014BDR2G
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-evh6mc_i/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ mc14014bdr2g.kicad_sym✓ mc14014bdr2g.kicad_mod✓ mc14014bdr2g.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2h ago
viewers mc14014bdr2g: viewers after the pinout correction · Ray 2h ago
mc14014bdr2g-etched.glb Publish 0.1.0 · Ray 2h ago
mc14014bdr2g-etched.step mc14014bdr2g: factory component page (tier=mfr) · Ray 2h ago
mc14014bdr2g-hero.glb Publish 0.1.1 · Ray 2h ago
mc14014bdr2g-hero.overlay.json Publish 0.1.1 · Ray 2h ago
mc14014bdr2g.glb Publish 0.1.0 · Ray 2h ago
mc14014bdr2g.kicad_mod Publish 0.1.0 · Ray 2h ago
mc14014bdr2g.kicad_sym Publish 0.1.1 · Ray 2h ago
mc14014bdr2g.lbr Publish 0.1.1 · Ray 2h ago
mc14014bdr2g.step Publish 0.1.0 · Ray 2h ago
package.json Publish 0.1.1 · Ray 2h ago
page.json mc14014bdr2g 0.1.1: pinout corrected (4 pins) · Ray 2h ago
README.md Publish 0.1.1 · Ray 2h ago
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 2h ago

MC14014BDR2G

onsemi · Shifting Register · SOIC-16

MC14014BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P8 input Parallel data input to stage 8, loaded synchronously on the clock when P/S is high (MC14014B), CMOS input from −0.5 V to VDD + 0.5 V.
2 Q6 output Sixth-stage shift register output, sourcing −0.51 mA min at VOH = 4.6 V and sinking 0.51 mA min at VOL = 0.4 V with VDD = 5 V and 25 °C.
3 Q8 output Eighth-stage serial data output, propagation delay 400 ns typ / 800 ns max from clock at VDD = 5 V and CL = 50 pF.
4 P4 input Parallel data input to stage 4, loaded synchronously on the clock when P/S is high.
5 P3 input Parallel data input to stage 3, loaded synchronously on the clock when P/S is high.
6 P2 input Parallel data input to stage 2, loaded synchronously on the clock when P/S is high.
7 P1 input Parallel data input to stage 1, loaded synchronously on the clock when P/S is high.
8 VSS power_in Ground and negative supply reference; all voltages are referenced to VSS.
9 P/S input Parallel/serial mode control: high selects parallel load from P1–P8 and low selects serial shift from DS; minimum pulse width 400 ns at VDD = 5 V.
10 C input Clock input that shifts data on the rising edge, 1.5 MHz min / 3.0 MHz typ at VDD = 5 V, with clock rise time 15 µs max at 5 V.
11 DS input Serial data input into stage 1 when P/S is low; setup time to clock 350 ns min at VDD = 5 V.
12 Q7 output Seventh-stage shift register output, CMOS push-pull drive.
13 P5 input Parallel data input to stage 5, loaded synchronously on the clock when P/S is high.
14 P6 input Parallel data input to stage 6, loaded synchronously on the clock when P/S is high.
15 P7 input Parallel data input to stage 7, loaded synchronously on the clock when P/S is high.
16 VDD power_in Positive supply, 3.0 Vdc to 18 Vdc operating range with an absolute maximum of −0.5 V to +18.0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage Range (absolute maximum) VDD -0.5 18 V Voltages referenced to VSS 1
Input or Output Voltage Range (DC or transient) Vin, Vout -0.5 V 1
Input or Output Current per pin (DC or transient) Iin, Iout 10 mA Per pin 1
Power Dissipation per package PD 500 mW Per package (Note 1); derate -7.0 mW/°C from 65 °C to 125 °C, D/DW package 1
Ambient Temperature Range TA -55 125 °C 1
Storage Temperature Range Tstg -65 150 °C 1
Lead Temperature TL 260 °C 8-second soldering 1
Supply Voltage Range VDD 3 18 V Stated in Features list 1
Output Voltage 0 Level VOL 0 0.05 Vdc VDD=5.0 Vdc; Vin = VDD or 0; TA=25 °C 3
Output Voltage 1 Level VOH 4.95 5 Vdc VDD=5.0 Vdc; Vin = 0 or VDD; TA=25 °C 3
Output Voltage 1 Level VOH 9.95 10 Vdc VDD=10 Vdc; Vin = 0 or VDD; TA=25 °C 3
Output Voltage 1 Level VOH 14.95 15 Vdc VDD=15 Vdc; Vin = 0 or VDD; TA=25 °C 3
Input Voltage 0 Level VIL 2.25 1.5 Vdc VDD=5.0 Vdc; VO = 4.5 or 0.5 Vdc; TA=25 °C 3
Input Voltage 0 Level VIL 4.5 3 Vdc VDD=10 Vdc; VO = 9.0 or 1.0 Vdc; TA=25 °C 3
Input Voltage 0 Level VIL 6.75 4 Vdc VDD=15 Vdc; VO = 13.5 or 1.5 Vdc; TA=25 °C 3
Input Voltage 1 Level VIH 3.5 2.75 Vdc VDD=5.0 Vdc; VO = 0.5 or 4.5 Vdc; TA=25 °C 3
Input Voltage 1 Level VIH 7 5.5 Vdc VDD=10 Vdc; VO = 1.0 or 9.0 Vdc; TA=25 °C 3
Input Voltage 1 Level VIH 11 8.25 Vdc VDD=15 Vdc; VO = 1.5 or 13.5 Vdc; TA=25 °C 3
Output Drive Current Source IOH -2.4 -4.2 mAdc VDD=5.0 Vdc; VOH = 2.5 Vdc; TA=25 °C 3
Output Drive Current Source IOH -0.51 -0.88 mAdc VDD=5.0 Vdc; VOH = 4.6 Vdc; TA=25 °C 3
Output Drive Current Source IOH -1.3 -2.25 mAdc VDD=10 Vdc; VOH = 9.5 Vdc; TA=25 °C 3
Output Drive Current Source IOH -3.4 -8.8 mAdc VDD=15 Vdc; VOH = 13.5 Vdc; TA=25 °C 3
Output Drive Current Sink IOL 0.51 0.88 mAdc VDD=5.0 Vdc; VOL = 0.4 Vdc; TA=25 °C 3
Output Drive Current Sink IOL 1.3 2.25 mAdc VDD=10 Vdc; VOL = 0.5 Vdc; TA=25 °C 3
Output Drive Current Sink IOL 3.4 8.8 mAdc VDD=15 Vdc; VOL = 1.5 Vdc; TA=25 °C 3
Input Current Iin 1e-05 0.1 Adc VDD=15 Vdc; TA=25 °C 3
Input Capacitance Cin 5 7.5 pF Vin = 0 3
Quiescent Current per package IDD 0.005 5 Adc Per package; VDD=5.0 Vdc; TA=25 °C 3
Quiescent Current per package IDD 0.01 10 Adc Per package; VDD=10 Vdc; TA=25 °C 3
Quiescent Current per package IDD 0.015 15 Adc Per package; VDD=15 Vdc; TA=25 °C 3
Output Rise and Fall Time tTLH, tTHL 100 200 ns VDD=5.0 Vdc; CL = 50 pF, TA = 25 °C 4
Output Rise and Fall Time tTLH, tTHL 50 100 ns VDD=10 Vdc; CL = 50 pF, TA = 25 °C 4
Output Rise and Fall Time tTLH, tTHL 40 80 ns VDD=15 Vdc; CL = 50 pF, TA = 25 °C 4
Propagation Delay Time (Clock to Q, P/S to Q) tPHL, tPLH 400 800 ns VDD=5.0 Vdc; CL = 50 pF, TA = 25 °C 4
Propagation Delay Time (Clock to Q, P/S to Q) tPHL, tPLH 170 340 ns VDD=10 Vdc; CL = 50 pF, TA = 25 °C 4
Propagation Delay Time (Clock to Q, P/S to Q) tPHL, tPLH 115 230 ns VDD=15 Vdc; CL = 50 pF, TA = 25 °C 4
Clock Frequency fcl 3 1.5 MHz VDD=5.0 Vdc; CL = 50 pF, TA = 25 °C 4
Clock Frequency fcl 6 3 MHz VDD=10 Vdc; CL = 50 pF, TA = 25 °C 4
Clock Frequency fcl 8 4 MHz VDD=15 Vdc; CL = 50 pF, TA = 25 °C 4
Clock Pulse Width tWH 400 150 ns VDD=5.0 Vdc; CL = 50 pF, TA = 25 °C 4
Clock Pulse Width tWH 175 75 ns VDD=10 Vdc; CL = 50 pF, TA = 25 °C 4
Clock Pulse Width tWH 135 40 ns VDD=15 Vdc; CL = 50 pF, TA = 25 °C 4
Parallel/Serial Control Pulse Width tWH 400 150 ns VDD=5.0 Vdc; CL = 50 pF, TA = 25 °C 4
Parallel/Serial Control Pulse Width tWH 175 75 ns VDD=10 Vdc; CL = 50 pF, TA = 25 °C 4
Parallel/Serial Control Pulse Width tWH 135 40 ns VDD=15 Vdc; CL = 50 pF, TA = 25 °C 4
Setup Time P/S to Clock tsu 200 100 ns VDD=5.0 Vdc; CL = 50 pF, TA = 25 °C 4
Setup Time P/S to Clock tsu 100 50 ns VDD=10 Vdc; CL = 50 pF, TA = 25 °C 4
Setup Time P/S to Clock tsu 80 40 ns VDD=15 Vdc; CL = 50 pF, TA = 25 °C 4
Setup Time Data (Parallel or Serial) to Clock or P/S tsu 350 150 ns VDD=5.0 Vdc; CL = 50 pF, TA = 25 °C 4
Setup Time Data (Parallel or Serial) to Clock or P/S tsu 80 50 ns VDD=10 Vdc; CL = 50 pF, TA = 25 °C 4
Setup Time Data (Parallel or Serial) to Clock or P/S tsu 60 30 ns VDD=15 Vdc; CL = 50 pF, TA = 25 °C 4
Hold Time Clock to P/S th 20 -2.5 ns VDD=5.0 Vdc; CL = 50 pF, TA = 25 °C 4
Hold Time Clock to P/S th 20 -10 ns VDD=10 Vdc; CL = 50 pF, TA = 25 °C 4
Hold Time Clock to P/S th 25 0 ns VDD=15 Vdc; CL = 50 pF, TA = 25 °C 4
Hold Time Clock to DS th 45 0 ns VDD=5.0 Vdc; CL = 50 pF, TA = 25 °C 4
Hold Time Clock to DS th 35 0 ns VDD=10 Vdc; CL = 50 pF, TA = 25 °C 4
Hold Time Clock to DS th 35 5 ns VDD=15 Vdc; CL = 50 pF, TA = 25 °C 4

CAD (KiCad official)

  • Symbol: MC14014BDR2G
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: mc14014bdr2g-etched.step / mc14014bdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc14014bdr2g.step / mc14014bdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (10 pp, sha256 b9cfde3fc92fe1a5, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF