MC14013BDR2G

{
  "schema_version": 1,
  "type": "component",
  "slug": "mc14013bdr2g",
  "title": "MC14013BDR2G",
  "brief": "onsemi Flip Flops, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "logic",
    "mc14013bdr2g"
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  "component": {
    "mpn": "MC14013BDR2G",
    "manufacturer": "onsemi",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Flip Flops",
    "datasheet": "https://www.onsemi.com/pdf/datasheet/mc14013b-d.pdf",
    "parts": {
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      "footprint": "mc14013bdr2g.kicad_mod",
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      "model_3d_plain": "mc14013bdr2g.glb",
      "model_3d_step": "mc14013bdr2g-etched.step",
      "model_3d_step_plain": "mc14013bdr2g.step",
      "lbr": "mc14013bdr2g.lbr"
    },
    "distributor_links": {
      "lcsc": "C56411"
    },
    "pins": [
      {
        "number": "1",
        "name": "QA",
        "type": "output",
        "description": "Flip-flop A true output. CMOS push-pull output; drives two low-power TTL loads or one LS-TTL load across the rated supply range (3.0-18 V)."
      },
      {
        "number": "2",
        "name": "QA_N",
        "type": "output",
        "description": "Flip-flop A complementary (Q-bar) output. Always the logical inverse of QA except in the Set=Reset=1 illegal state where both outputs go high."
      },
      {
        "number": "3",
        "name": "CA",
        "type": "input",
        "description": "Flip-flop A clock input. Data on DA is transferred to QA on the positive-going (rising) edge of this clock. CMOS input with diode protection; VIH >= 0.7*VDD, VIL <= 0.3*VDD."
      },
      {
        "number": "4",
        "name": "RA",
        "type": "input",
        "description": "Flip-flop A asynchronous Direct Reset input, active-high. Forces QA=0 and QA_N=1 regardless of Clock/Data. Tie low (VSS) during normal edge-clocked operation."
      },
      {
        "number": "5",
        "name": "DA",
        "type": "input",
        "description": "Flip-flop A Data input. The logic level present on DA is captured to QA on the rising edge of CA. Setup/hold: 40 ns / 40 ns at VDD=5 V (min)."
      },
      {
        "number": "6",
        "name": "SA",
        "type": "input",
        "description": "Flip-flop A asynchronous Direct Set input, active-high. Forces QA=1 and QA_N=0 regardless of Clock/Data. Tie low (VSS) during normal edge-clocked operation."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference. All input/output voltages are referenced to VSS."
      },
      {
        "number": "8",
        "name": "SB",
        "type": "input",
        "description": "Flip-flop B asynchronous Direct Set input, active-high. Forces QB=1 and QB_N=0 regardless of Clock/Data. Tie low (VSS) during normal edge-clocked operation."
      },
      {
        "number": "9",
        "name": "DB",
        "type": "input",
        "description": "Flip-flop B Data input. The logic level present on DB is captured to QB on the rising edge of CB. Setup/hold: 40 ns / 40 ns at VDD=5 V (min)."
      },
      {
        "number": "10",
        "name": "RB",
        "type": "input",
        "description": "Flip-flop B asynchronous Direct Reset input, active-high. Forces QB=0 and QB_N=1 regardless of Clock/Data. Tie low (VSS) during normal edge-clocked operation."
      },
      {
        "number": "11",
        "name": "CB",
        "type": "input",
        "description": "Flip-flop B clock input. Data on DB is transferred to QB on the positive-going (rising) edge of this clock. Max clock frequency 2 MHz @ 5 V, 5 MHz @ 10 V, 7 MHz @ 15 V."
      },
      {
        "number": "12",
        "name": "QB_N",
        "type": "output",
        "description": "Flip-flop B complementary (Q-bar) output. Always the logical inverse of QB except in the Set=Reset=1 illegal state where both outputs go high."
      },
      {
        "number": "13",
        "name": "QB",
        "type": "output",
        "description": "Flip-flop B true output. CMOS push-pull output; drives two low-power TTL loads or one LS-TTL load across the rated supply range (3.0-18 V)."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply input. Operating range 3.0 V to 18 V (absolute max -0.5 to +18.0 V). Bypass locally to VSS."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.onsemi.com/pdf/datasheet/mc14013b-d.pdf",
        "pages": 8,
        "sha256": "d026165b363be4d9",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -3.81
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-14_3.9x8.7mm_P1.27mm@sha256:a885b619b22880c9",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "CD4013",
      "logic_family": "CD4000",
      "function_code": "4013",
      "function_class": "Flip-Flop",
      "function_name": "Dual D Flip-Flop",
      "manufacturer": "Onsemi (Motorola legacy)",
      "is_specialty": false
    },
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        "units": "mm",
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        "seat": "z = 0",
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          8.7,
          1.75
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "mc14013bdr2g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
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        "zmin_mm": 0,
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        "sha256": "ec9378081bcd32e3f6ebcecb35e9c43099a7d49c459775d77dd334639152354b",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "onsemi",
      "Package": "SOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "sections": [
    "hero",
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    "readme",
    "breadcrumbs",
    "info"
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  "discovery_triggers": [
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  "discovery_pitch": "MC14013BDR2G (onsemi) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
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    "path": "docs/hero.png"
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  "files": [
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    "README.md",
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    "mc14013bdr2g.step",
    "mc14013bdr2g-etched.step",
    "mc14013bdr2g.lbr",
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  "visibility": {
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  "variants": [
    {
      "mpn": "MC14013BDR2GDG",
      "kind": "packaging"
    },
    {
      "mpn": "MC14013BDR2G",
      "kind": "packaging"
    },
    {
      "mpn": "MC14013BDR2GDTR2G",
      "kind": "packaging"
    },
    {
      "mpn": "MC14013BDR2GFG",
      "kind": "packaging"
    },
    {
      "mpn": "MC14013BDR2GFELG",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-28T18:41:22.038Z"
}