component

MC14008BDR2G

Public Made by Adom

by adom

onsemi Special Logic ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icsmc14008bdr2gfactory-2.0.0extractor-text

Verified MC14008BDR2G

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MC14008BDR2G · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 8-page datasheet
  • ✓distributor: lcsc C903923, digikey MC14008BDR2GOSTR-ND, mouser 863-MC14008BDR2G
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-suhby8hv/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.7)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ mc14008bdr2g.kicad_sym✓ mc14008bdr2g.kicad_mod✓ mc14008bdr2g.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7h ago
viewers mc14008bdr2g: viewers · Ray 7h ago
mc14008bdr2g-etched.glb Publish 0.1.0 · Ray 7h ago
mc14008bdr2g-etched.step mc14008bdr2g: factory component page (tier=mfr) · Ray 7h ago
mc14008bdr2g-hero.glb mc14008bdr2g: hero GLB from the etched model (keeps the MPN mark) · Ray 7h ago
mc14008bdr2g-hero.overlay.json Publish 0.1.0 · Ray 7h ago
mc14008bdr2g.glb Publish 0.1.0 · Ray 7h ago
mc14008bdr2g.kicad_mod Publish 0.1.0 · Ray 7h ago
mc14008bdr2g.kicad_sym Publish 0.1.0 · Ray 7h ago
mc14008bdr2g.lbr Publish 0.1.0 · Ray 7h ago
mc14008bdr2g.step Publish 0.1.0 · Ray 7h ago
package.json Publish 0.1.0 · Ray 7h ago
page.json Set visibility: public · Ray 7h ago
README.md Publish 0.1.0 · Ray 7h ago
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 7h ago

MC14008BDR2G

onsemi · Special Logic ICs · SOIC-16

MC14008BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A4 input Bit-4 operand A input of the 4-bit full adder; unused inputs must be tied to VSS or VDD, and input voltage must stay between VSS and VDD.
2 B3 input Bit-3 operand B input of the 4-bit full adder; unused inputs must be tied to VSS or VDD, and input voltage must stay between VSS and VDD.
3 A3 input Bit-3 operand A input of the 4-bit full adder; unused inputs must be tied to VSS or VDD, and input voltage must stay between VSS and VDD.
4 B2 input Bit-2 operand B input of the 4-bit full adder; unused inputs must be tied to VSS or VDD, and input voltage must stay between VSS and VDD.
5 A2 input Bit-2 operand A input of the 4-bit full adder; unused inputs must be tied to VSS or VDD, and input voltage must stay between VSS and VDD.
6 B1 input Bit-1 operand B input of the 4-bit full adder; unused inputs must be tied to VSS or VDD, and input voltage must stay between VSS and VDD.
7 A1 input Bit-1 operand A input of the 4-bit full adder; unused inputs must be tied to VSS or VDD, and input voltage must stay between VSS and VDD.
8 VSS power_in Circuit reference (ground) pin to which all voltages are referenced; the absolute maximum DC supply is +18.0 V above VSS.
9 Cin input Carry-input to the least significant full-adder stage; unused inputs must be tied to VSS or VDD.
10 S1 output Sum output of adder stage 1; all outputs are buffered.
11 S2 output Sum output of adder stage 2; all outputs are buffered.
12 S3 output Sum output of adder stage 3; all outputs are buffered.
13 S4 output Sum output of adder stage 4; all outputs are buffered.
14 Cout output High-speed parallel look-ahead carry output; all outputs are buffered and unused outputs must be left open.
15 B4 input Bit-4 operand B input of the 4-bit full adder; unused inputs must be tied to VSS or VDD, and input voltage must stay between VSS and VDD.
16 VDD power_in Positive supply pin; supply range is 3.0 Vdc to 18 Vdc, with absolute maximum DC supply voltage range of −0.5 to +18.0 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage Range VDD -0.5 18 V Voltages referenced to VSS 1
Input or Output Voltage Range (DC or Transient) Vin, Vout -0.5 V Upper limit printed as VDD + 0.5 V; referenced to VSS 1
Input or Output Current (DC or Transient) per pin Iin, Iout -10 10 mA DC or transient, per pin 1
Power Dissipation, per Package PD 500 mW Note 1: D/DW package derate -7.0 mW/°C from 65°C to 125°C 1
Ambient Temperature Range TA -55 125 °C 1
Storage Temperature Range Tstg -65 150 °C 1
Lead Temperature TL 260 °C 8-second soldering 1
Supply Voltage Range (from Features list) VDD 3 18 Vdc Stated as 3.0 Vdc to 18 Vdc in Features; no recommended operating table printed 1
Output Voltage '0' Level, VDD 5.0 Vdc VOL 0.05 Vdc Vin = VDD or 0; TA = −55°C 3
Output Voltage '0' Level, VDD 5.0 Vdc VOL 0 0.05 Vdc Vin = VDD or 0; TA = 25°C 3
Output Voltage '0' Level, VDD 10 Vdc VOL 0.05 Vdc Vin = VDD or 0; TA = −55°C 3
Output Voltage '0' Level, VDD 10 Vdc VOL 0 0.05 Vdc Vin = VDD or 0; TA = 25°C 3
Output Voltage '0' Level, VDD 15 Vdc VOL 0.05 Vdc Vin = VDD or 0; TA = −55°C 3
Output Voltage '0' Level, VDD 15 Vdc VOL 0 0.05 Vdc Vin = VDD or 0; TA = 25°C 3
Output Voltage '1' Level, VDD 5.0 Vdc VOH 4.95 Vdc Vin = 0 or VDD; TA = −55°C 3
Output Voltage '1' Level, VDD 5.0 Vdc VOH 4.95 5 Vdc Vin = 0 or VDD; TA = 25°C 3
Output Voltage '1' Level, VDD 10 Vdc VOH 9.95 Vdc Vin = 0 or VDD; TA = −55°C 3
Output Voltage '1' Level, VDD 10 Vdc VOH 9.95 10 Vdc Vin = 0 or VDD; TA = 25°C 3
Output Voltage '1' Level, VDD 15 Vdc VOH 14.95 Vdc Vin = 0 or VDD; TA = −55°C 3
Output Voltage '1' Level, VDD 15 Vdc VOH 14.95 15 Vdc Vin = 0 or VDD; TA = 25°C 3
Input Voltage '0' Level, VDD 5.0 Vdc VIL 1.5 Vdc VO = 4.5 or 0.5 Vdc; TA = −55°C 3
Input Voltage '0' Level, VDD 5.0 Vdc VIL 2.25 1.5 Vdc VO = 4.5 or 0.5 Vdc; TA = 25°C 3
Input Voltage '0' Level, VDD 10 Vdc VIL 3 Vdc VO = 9.0 or 1.0 Vdc; TA = −55°C 3
Input Voltage '0' Level, VDD 10 Vdc VIL 4.5 3 Vdc VO = 9.0 or 1.0 Vdc; TA = 25°C 3
Input Voltage '0' Level, VDD 15 Vdc VIL 4 Vdc VO = 13.5 or 1.5 Vdc; TA = −55°C 3
Input Voltage '0' Level, VDD 15 Vdc VIL 6.75 4 Vdc VO = 13.5 or 1.5 Vdc; TA = 25°C 3
Input Voltage '1' Level, VDD 5.0 Vdc VIH 3.5 Vdc VO = 0.5 or 4.5 Vdc; TA = −55°C 3
Input Voltage '1' Level, VDD 5.0 Vdc VIH 3.5 2.75 Vdc VO = 0.5 or 4.5 Vdc; TA = 25°C 3
Input Voltage '1' Level, VDD 10 Vdc VIH 7 Vdc VO = 1.0 or 9.0 Vdc; TA = −55°C 3
Input Voltage '1' Level, VDD 10 Vdc VIH 7 5.5 Vdc VO = 1.0 or 9.0 Vdc; TA = 25°C 3
Input Voltage '1' Level, VDD 15 Vdc VIH 11 Vdc VO = 1.5 or 13.5 Vdc; TA = −55°C 3
Input Voltage '1' Level, VDD 15 Vdc VIH 11 8.25 Vdc VO = 1.5 or 13.5 Vdc; TA = 25°C 3
Quiescent Current (Per Package), VDD 5.0 Vdc IDD 5 Adc VDD = 5.0 Vdc; TA = −55°C 3
Quiescent Current (Per Package), VDD 5.0 Vdc IDD 0.005 5 Adc VDD = 5.0 Vdc; TA = 25°C 3
Quiescent Current (Per Package), VDD 5.0 Vdc IDD 150 Adc VDD = 5.0 Vdc; TA = 125°C 3
Quiescent Current (Per Package), VDD 10 Vdc IDD 10 Adc VDD = 10 Vdc; TA = −55°C 3
Quiescent Current (Per Package), VDD 10 Vdc IDD 0.01 10 Adc VDD = 10 Vdc; TA = 25°C 3
Quiescent Current (Per Package), VDD 10 Vdc IDD 300 Adc VDD = 10 Vdc; TA = 125°C 3
Quiescent Current (Per Package), VDD 15 Vdc IDD 20 Adc VDD = 15 Vdc; TA = −55°C 3
Quiescent Current (Per Package), VDD 15 Vdc IDD 0.015 20 Adc VDD = 15 Vdc; TA = 25°C 3
Quiescent Current (Per Package), VDD 15 Vdc IDD 600 Adc VDD = 15 Vdc; TA = 125°C 3
Input Capacitance Cin 5 7.5 pF Vin = 0 3
Propagation Delay Time, Sum In to Sum Out, VDD 5.0 Vdc tPLH, tPHL 400 800 ns CL = 50 pF, TA = 25°C 4
Propagation Delay Time, Sum In to Sum Out, VDD 10 Vdc tPLH, tPHL 160 320 ns CL = 50 pF, TA = 25°C 4
Propagation Delay Time, Sum In to Sum Out, VDD 15 Vdc tPLH, tPHL 115 230 ns CL = 50 pF, TA = 25°C 4
Propagation Delay Time, Carry In to Carry Out, VDD 5.0 Vdc tPLH, tPHL 170 340 ns CL = 50 pF, TA = 25°C 4
Propagation Delay Time, Carry In to Carry Out, VDD 10 Vdc tPLH, tPHL 75 150 ns CL = 50 pF, TA = 25°C 4
Propagation Delay Time, Carry In to Carry Out, VDD 15 Vdc tPLH, tPHL 55 110 ns CL = 50 pF, TA = 25°C 4

CAD (KiCad official)

  • Symbol: MC14008BDR2G
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: mc14008bdr2g-etched.step / mc14008bdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc14008bdr2g.step / mc14008bdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 7952d976f328b1c9, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF