component
MC14001BDR2G
Public Made by Adomby adom
onsemi Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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mc14001bdr2g: factory component page (tier=mfr)
3 files changed
+45−39
README.md+21−18@@ -8,20 +8,20 @@ MC14001BDR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted fr | Pin | Name | Type | Function | |---|---|---|---|-| 1 | IN1A | input | Gate A input 1. CMOS logic input to NOR gate A; high impedance, VIH >= 3.5 V at VDD = 5 V; unused inputs of NOR gates must be tied to VSS. |-| 2 | IN2A | input | Gate A input 2. CMOS logic input to NOR gate A; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS. |-| 3 | OUTA | output | Gate A output. Buffered CMOS output equal to NOR(IN1A, IN2A). Drives two LSTTL loads; IOH ~ -0.88 mA typ at VOH = 4.6 V, VDD = 5 V. |-| 4 | OUTB | output | Gate B output. Buffered CMOS output equal to NOR(IN1B, IN2B). Drives two LSTTL loads; IOH ~ -0.88 mA typ at VOH = 4.6 V, VDD = 5 V. |-| 5 | IN1B | input | Gate B input 1. CMOS logic input to NOR gate B; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS. |-| 6 | IN2B | input | Gate B input 2. CMOS logic input to NOR gate B; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS. |-| 7 | VSS | power_in | Negative supply / ground reference. All voltages referenced to VSS; typically 0 V. |-| 8 | IN1C | input | Gate C input 1. CMOS logic input to NOR gate C; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS. |-| 9 | IN2C | input | Gate C input 2. CMOS logic input to NOR gate C; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS. |-| 10 | OUTC | output | Gate C output. Buffered CMOS output equal to NOR(IN1C, IN2C). Drives two LSTTL loads; IOH ~ -0.88 mA typ at VOH = 4.6 V, VDD = 5 V. |-| 11 | OUTD | output | Gate D output. Buffered CMOS output equal to NOR(IN1D, IN2D). Drives two LSTTL loads; IOH ~ -0.88 mA typ at VOH = 4.6 V, VDD = 5 V. |-| 12 | IN1D | input | Gate D input 1. CMOS logic input to NOR gate D; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS. |-| 13 | IN2D | input | Gate D input 2. CMOS logic input to NOR gate D; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS. |-| 14 | VDD | power_in | Positive supply. Operating range 3.0 V to 18 V (absolute max -0.5 V to +18 V). Quiescent current IDD ~ 0.5 uA typ per package at VDD = 10 V, 25 C. |+| 1 | IN1A | input | Gate A input 1. CMOS logic input, V_IL max 1.5 V @ VDD=5 V, V_IH min 3.5 V @ VDD=5 V. Input current ±0.1 µA typ. |+| 2 | IN2A | input | Gate A input 2. CMOS logic input for the second input of NOR gate A. Unused inputs must be tied to VSS or VDD. |+| 3 | OUTA | output | Gate A output. NOR of IN1A and IN2A. Drives two low-power TTL loads; source/sink drive typically ~0.88 mA @ VDD=5 V. |+| 4 | OUTB | output | Gate B output. NOR of IN1B and IN2B. |+| 5 | IN1B | input | Gate B input 1. CMOS logic input. |+| 6 | IN2B | input | Gate B input 2. CMOS logic input. |+| 7 | VSS | power_in | Negative supply / ground reference. Typically 0 V. All voltages in the datasheet are referenced to VSS. |+| 8 | IN1C | input | Gate C input 1. CMOS logic input. |+| 9 | IN2C | input | Gate C input 2. CMOS logic input. |+| 10 | OUTC | output | Gate C output. NOR of IN1C and IN2C. |+| 11 | OUTD | output | Gate D output. NOR of IN1D and IN2D. |+| 12 | IN1D | input | Gate D input 1. CMOS logic input. |+| 13 | IN2D | input | Gate D input 2. CMOS logic input. |+| 14 | VDD | power_in | Positive supply voltage. 3.0 V to 18 V operating range (absolute max −0.5 V to +18 V). Bypass locally with a ceramic capacitor. | ## Key specifications @@ -34,10 +34,13 @@ MC14001BDR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted fr ## Ordering variants -- `MC14001BDR2GDR2G`-- `MC14001BDR2GDG`-- `MC14001BDR2GDTR2G`-- `MC14001BDR2GDTG`+- `MC14001BDR2GMC14001BDG`+- `MC14001BDR2G`+- `MC14001BDR2GNLV14001BDG`+- `MC14001BDR2GNLV14001BDR2G`+- `MC14001BDR2GMC14001BDTR2G`+- `MC14001BDR2GNLV14001BDTR2G`+- `MC14001BDR2GMC14001BFELG` ## CAD (KiCad official)
mc14001bdr2g.lbr+9−3@@ -50,7 +50,7 @@ <layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> </layers> <library>-<description></description>+<description>onsemi Gates, SOIC-14</description> <packages> <package name="SOIC-14_3.9x8.7mm_P1.27mm"> <description>SOIC-14, 3.9 x 8.7 mm, 1.27 mm pitch</description>@@ -92,6 +92,7 @@ </packages> <symbols> <symbol name="MC14001BDR2G">+ <description>onsemi Gates, SOIC-14</description> <wire x1="-12.7" y1="10.16" x2="12.7" y2="10.16" width="0.254" layer="94"/> <wire x1="12.7" y1="10.16" x2="12.7" y2="-10.16" width="0.254" layer="94"/> <wire x1="12.7" y1="-10.16" x2="-12.7" y2="-10.16" width="0.254" layer="94"/>@@ -116,7 +117,7 @@ </symbols> <devicesets> <deviceset name="MC14001BDR2G" prefix="U">- <description></description>+ <description>onsemi Gates, SOIC-14</description> <gates> <gate name="G$1" symbol="MC14001BDR2G" x="0" y="0"/> </gates>@@ -138,7 +139,12 @@ <connect gate="G$1" pin="IN2C" pad="9"/> <connect gate="G$1" pin="IN1C" pad="8"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="MC14001BDR2G" constant="no"/>+ <attribute name="MANUFACTURER" value="onsemi" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+15−18@@ -32,85 +32,85 @@ "number": "1", "name": "IN1A", "type": "input",- "description": "Gate A input 1. CMOS logic input to NOR gate A; high impedance, VIH >= 3.5 V at VDD = 5 V; unused inputs of NOR gates must be tied to VSS."+ "description": "Gate A input 1. CMOS logic input, V_IL max 1.5 V @ VDD=5 V, V_IH min 3.5 V @ VDD=5 V. Input current \u00b10.1 \u00b5A typ." }, { "number": "2", "name": "IN2A", "type": "input",- "description": "Gate A input 2. CMOS logic input to NOR gate A; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS."+ "description": "Gate A input 2. CMOS logic input for the second input of NOR gate A. Unused inputs must be tied to VSS or VDD." }, { "number": "3", "name": "OUTA", "type": "output",- "description": "Gate A output. Buffered CMOS output equal to NOR(IN1A, IN2A). Drives two LSTTL loads; IOH ~ -0.88 mA typ at VOH = 4.6 V, VDD = 5 V."+ "description": "Gate A output. NOR of IN1A and IN2A. Drives two low-power TTL loads; source/sink drive typically ~0.88 mA @ VDD=5 V." }, { "number": "4", "name": "OUTB", "type": "output",- "description": "Gate B output. Buffered CMOS output equal to NOR(IN1B, IN2B). Drives two LSTTL loads; IOH ~ -0.88 mA typ at VOH = 4.6 V, VDD = 5 V."+ "description": "Gate B output. NOR of IN1B and IN2B." }, { "number": "5", "name": "IN1B", "type": "input",- "description": "Gate B input 1. CMOS logic input to NOR gate B; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS."+ "description": "Gate B input 1. CMOS logic input." }, { "number": "6", "name": "IN2B", "type": "input",- "description": "Gate B input 2. CMOS logic input to NOR gate B; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS."+ "description": "Gate B input 2. CMOS logic input." }, { "number": "7", "name": "VSS", "type": "power_in",- "description": "Negative supply / ground reference. All voltages referenced to VSS; typically 0 V."+ "description": "Negative supply / ground reference. Typically 0 V. All voltages in the datasheet are referenced to VSS." }, { "number": "8", "name": "IN1C", "type": "input",- "description": "Gate C input 1. CMOS logic input to NOR gate C; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS."+ "description": "Gate C input 1. CMOS logic input." }, { "number": "9", "name": "IN2C", "type": "input",- "description": "Gate C input 2. CMOS logic input to NOR gate C; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS."+ "description": "Gate C input 2. CMOS logic input." }, { "number": "10", "name": "OUTC", "type": "output",- "description": "Gate C output. Buffered CMOS output equal to NOR(IN1C, IN2C). Drives two LSTTL loads; IOH ~ -0.88 mA typ at VOH = 4.6 V, VDD = 5 V."+ "description": "Gate C output. NOR of IN1C and IN2C." }, { "number": "11", "name": "OUTD", "type": "output",- "description": "Gate D output. Buffered CMOS output equal to NOR(IN1D, IN2D). Drives two LSTTL loads; IOH ~ -0.88 mA typ at VOH = 4.6 V, VDD = 5 V."+ "description": "Gate D output. NOR of IN1D and IN2D." }, { "number": "12", "name": "IN1D", "type": "input",- "description": "Gate D input 1. CMOS logic input to NOR gate D; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS."+ "description": "Gate D input 1. CMOS logic input." }, { "number": "13", "name": "IN2D", "type": "input",- "description": "Gate D input 2. CMOS logic input to NOR gate D; high impedance, VIH >= 3.5 V at VDD = 5 V; unused NOR-gate inputs must be tied to VSS."+ "description": "Gate D input 2. CMOS logic input." }, { "number": "14", "name": "VDD", "type": "power_in",- "description": "Positive supply. Operating range 3.0 V to 18 V (absolute max -0.5 V to +18 V). Quiescent current IDD ~ 0.5 uA typ per package at VDD = 10 V, 25 C."+ "description": "Positive supply voltage. 3.0 V to 18 V operating range (absolute max \u22120.5 V to +18 V). Bypass locally with a ceramic capacitor." } ], "provenance": {@@ -174,8 +174,5 @@ "docs/mc14001bdr2g-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": {- "public": true- }+ ] }