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MAX9919FASA+

Analog Devices Inc./Maxim Integrated · Current-Sensing Amplifiers · SOIC-8-EP

MAX9919FASA+ from Analog Devices Inc./Maxim Integrated, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RS+ input Positive current-sensing input; the power side connects to the external sense resistor.
2 RS- input Negative current-sensing input; the load side connects to the external sense resistor.
3 SHDN input Active-high shutdown input; connect to GND for normal operation, and SHDN to GND is rated -0.3V to +20V.
4 GND power_in Ground.
5 OUT output Current-sense output; VOUT is proportional to VSENSE.
6 FB input Feedback input for setting gain on the MAX9918 and MAX9920; leave unconnected for the MAX9919 for proper operation.
7 REFIN input Reference input; set to VCC/2 for bidirectional operation or to GND for unidirectional operation.
8 VCC power_in 5V supply voltage input, specified over 4.5V to 5.5V; bypass VCC to GND with a 0.1µF capacitor.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices Inc./Maxim Integrated
Package SOIC-8-EP
Category Operational Amplifier/Comparator
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC to GND VCC -0.3 6 V 2
RS+, RS- to GND -30 80 V VCC = 5V 2
RS+, RS- to GND -15 80 V VCC = 0V, 15 minutes 2
Differential Input Voltage (VRS+ - VRS-) MAX9919 -15 15 V Continuous 2
SHDN to GND SHDN -0.3 20 V 2
Continuous Power Dissipation 1951.2 mW TA = +70°C, 8-Pin SO-EP, derate 24.4mW/°C above +70°C 2
Junction Temperature 150 °C 2
Storage Temperature Range -65 150 °C 2
Lead Temperature (soldering) 300 °C 10s 2
Soldering Temperature (reflow) 260 °C 2
Junction-to-Ambient Thermal Resistance, Four-Layer Board θJA 41 °C/W JESD51-7 four-layer board 2
Junction-to-Case Thermal Resistance, Four-Layer Board θJC 7 °C/W JESD51-7 four-layer board 2
Supply Voltage Range VCC 4.5 5.5 V Inferred from PSRR test 6
Operating Temperature Range TA -40 125 °C Fully specified over temperature range 1
Input Offset Voltage VOS -0.4 0.18 0.4 mV VRS+ = VRS- = +14V, VREFIN = 0V, TA = +25°C 3
Input Offset Voltage VOS -0.9 0.18 0.9 mV VRS+ = VRS- = +14V, VREFIN = 0V, TA = -40°C to +125°C 3
Input Offset Voltage VOS -0.4 0.11 0.4 mV VRS+ = VRS- = -2V, VREFIN = 0V, TA = +25°C 3
Input Offset Voltage VOS -1 0.11 1 mV VRS+ = VRS- = -2V, VREFIN = 0V, TA = -40°C to +125°C 3
Common-Mode Rejection Ratio CMRR 80 dB -2V ≤ VCM ≤ +14V 4
Common-Mode Rejection Ratio CMRR 96 dB -20V ≤ VCM ≤ +75V 4
Input Bias Current IRS+, IRS- -175 175 µA -20V ≤ VCM ≤ +75V, TA = +25°C 4
Input Bias Current IRS+, IRS- -250 250 µA -20V ≤ VCM ≤ +75V, TA = -40°C to +125°C 4
Input Offset Current -8 0 8 µA (IRS+ - IRS-) 4
Input Leakage Current in Shutdown -30 30 µA -20V ≤ VCM ≤ +75V, VSHDN = VCC = 5V 4
Input Leakage Current -30 30 µA VRS+ = VRS- = +14V, +75V, VCC = 0V 4
Gain Error GE -0.45 0.13 0.45 % VRS+ = VRS- = +14V, VREFIN = 0V, TA = +25°C 5
Gain Error GE -1.2 1.2 % VRS+ = VRS- = +14V, VREFIN = 0V, TA = -40°C to +125°C 5
Gain Error GE -0.45 0.1 0.45 % VRS+ = VRS- = -2V, VREFIN = 0V, TA = +25°C 5
Gain Error GE -0.9 0.9 % VRS+ = VRS- = -2V, VREFIN = 0V, TA = -40°C to +125°C 5
Output-Voltage High VCC - VOH 3 10 mV VSENSE = 200mV, RL = 100kΩ to GND 5
Output-Voltage High VCC - VOH 12 40 mV VSENSE = 200mV, RL = 10kΩ to GND 5
Output-Voltage Low VOL 3 10 mV VSENSE = -200mV, RL = 100kΩ to VCC 5
Output-Voltage Low VOL 10 40 mV VSENSE = -200mV, RL = 10kΩ to VCC 5
REFIN Voltage Range 0 V Inferred from REFIN CMRR test; max VCC - 1.9 (not numeric) 5
REFIN Common-Mode Rejection Ratio REFINCMRR 82 103 dB 0V ≤ VREFIN ≤ (VCC - 1.9V) 6
REFIN Current IREFIN -100 100 µA VRS+ = VRS- = ±50mV 6
SHDN Logic-High VIH 2 V 6
SHDN Logic-Low VIL 0.8 V 6
SHDN Logic Input Current 5 µA 0 ≤ VSHDN ≤ VCC 6
Power-Supply Rejection Ratio PSRR 74 103 dB MAX9919_, 4.5V ≤ VCC ≤ 5.5V 6
Supply Current ICC 0.7 1.2 mA VRS+ = VRS- = +14V, TA = +25°C 6
Supply Current ICC 1.5 mA VRS+ = VRS- = +14V, TA = -40°C to +125°C 6
Supply Current ICC 1 1.6 mA VRS+ = VRS- = -2V, TA = +25°C 6
Supply Current ICC 2.2 mA VRS+ = VRS- = -2V, TA = -40°C to +125°C 6
Shutdown Supply Current ICC_SHDN 0.5 10 µA VSHDN = VCC = 5V 6
Max Capacitive Load Stability 50 pF No sustained oscillations 7

CAD (KiCad official)

  • Symbol: MAX9919FASA+
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: max9919fasa-etched.step / max9919fasa-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max9919fasa.step / max9919fasa.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc./Maxim Integrated datasheet (19 pp, sha256 f62a520074711291, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF