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Contents

README

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MAX9850ETI+T

Analog Devices Inc./Maxim Integrated · Audio Power OpAmps · TQFN-28(5x5)

MAX9850ETI+T from Analog Devices Inc./Maxim Integrated, in a TQFN-28(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LRCLK bidirectional Digital audio left-right clock that sets whether SDIN data goes to the left or right channel; it is an input in slave mode and an output in master mode.
2 BCLK bidirectional Digital audio bit clock that is an input in slave mode and an output in master mode.
3 SDIN input Digital audio serial data input.
4 DVDD power_in Digital power-supply input, specified at 1.8V to 3.6V, to be bypassed to DGND with a 1µF ceramic capacitor.
5 MCLK input Master clock input from which all internal digital clocks are derived (up to 40MHz per the features list).
6 DGND power_in Digital ground.
7 ADD input I2C address-select input; connect to AGND, AVDD, or SDA to select one of three possible I2C addresses.
8 GPIO bidirectional General-purpose input/output configured as input or output through the GPIO register, and can generate an interrupt when configured as an output.
9 INR input Right-channel line input that is mixed with the right DAC output.
10 INL input Left-channel line input that is mixed with the left DAC output.
11 OUTR output Line-level right-channel output biased at AGND.
12 OUTL output Line-level left-channel output biased at AGND.
13 REF output Reference output, to be bypassed to AGND with a 1µF ceramic capacitor.
14 AGND power_in Analog ground.
15 NREG power_out Line-output negative regulator output, to be bypassed to AGND with a 1µF capacitor.
16 PREG power_out Line-output positive regulator output, to be bypassed to AGND with a 1µF capacitor.
17 AVDD power_in Analog power supply, specified at 1.8V to 3.6V, to be bypassed to AGND with a 1µF ceramic capacitor.
18 HPR output Right-channel DirectDrive headphone output biased at AGND.
19 HPL output Left-channel DirectDrive headphone output biased at AGND.
20 SVSS power_in Headphone amplifier negative power-supply input, to be connected to PVSS.
21 HPS input Headphone sense input for automatic headphone sensing, to be connected to the jack control pin and left floating if unused.
22 PVSS power_out Inverting charge-pump output, to be bypassed to PGND with a 2.2µF ceramic capacitor and connected to SVSS to supply the headphone amplifiers.
23 C1N passive Charge-pump flying capacitor negative terminal; a 0.47µF ceramic capacitor connects between C1N and C1P.
24 PGND power_in Charge-pump ground.
25 C1P passive Charge-pump flying capacitor positive terminal; a 0.47µF ceramic capacitor connects between C1P and C1N.
26 PVDD power_in Charge-pump and headphone amplifier positive power-supply input, to be bypassed to PGND with 1µF and connected to AVDD for normal operation.
27 SCL input I2C-compatible serial clock input.
28 SDA bidirectional I2C-compatible serial data input/output.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices Inc./Maxim Integrated
Package TQFN-28(5x5)
Category Operational Amplifier/Comparator
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog Supply Voltage (AVDD, PVDD) AVDD, PVDD 1.8 3.6 V AVDD = PVDD 2
Digital Supply Voltage DVDD 1.8 3.6 V 2
Analog Supply Current AIDD 5.5 7.7 mA Full operation (Note 2), no headphone or line output load, AVDD = 1.8V 2
Analog Supply Current AIDD 3.5 5.3 mA Full operation (Note 2), headphones disabled, AVDD = 1.8V 2
Digital Supply Current DIDD 2.1 2.9 mA Full operation (Note 2), no line output load, DVDD = 1.8V 2
Analog Shutdown Current AISHDN 1.5 10 µA IAVDD + IPVDD, AVDD = PVDD = 1.8V 2
Digital Shutdown Current DISHDN 0.3 5 µA Static digital interface, DVDD = 1.8V 2
0dBFS Output Voltage VOUT_FS 1.85 1.95 2.05 VP-P 2
Line Output Offset Voltage VOS_LINE -15 0 15 mV 3
Channel-to-Channel Gain Matching ΔAV/AV -0.04 0.04 dB OUTL to OUTR, OUTR to OUTL 3
Sampling Frequency Range fS 8 48 kHz 3
MCLK Frequency fMCLK 8.448 40 MHz 3
Frequency Response FR -0.1 0.1 dB 10Hz to 20kHz 3
Line Input Voltage VIN_LINE -1 1 V 3
IN_ to OUT_ Gain AV_LINE -1.05 -1 -0.95 V/V 3
Line Input Bias Voltage VBIAS_LINE -15 0 15 mV 3
INL and INR Input Resistance RIN_LINE 10 22 kΩ 3
Headphone 0dBFS Full-Scale Output Voltage VOUT_FS 1.16 1.23 1.3 VRMS Volume = +5dB, HP unloaded 4
Line In to HP Output Voltage Gain AV_HP 1.34 1.41 1.48 V/V Volume = +3dB, HP unloaded 4
Headphone Output Offset Voltage VOS_HP -15 15 mV Volume = -11.5dB, TA = +25°C 4
Headphone Output Offset Voltage VOS_HP -25 25 mV Volume = -11.5dB, TA = TMIN to TMAX 4
Maximum Capacitive Load CL 150 pF No sustained oscillations 4
Channel-to-Channel Gain Matching (headphone) ΔAV/AV -0.05 0.05 dB 4
Internal Charge-Pump Oscillator Frequency fCP 550 667 775 kHz 4
Charge-Pump Operating Frequency Range 550 775 kHz Charge-pump clock derived from MCLK 4
Volume Control Range -73.5 6 dB 4
Input Leakage Current IIH, IIL -10 10 µA VIH = DVDD, VIL = DGND 5
SCL Serial Clock Frequency fSCL 0 400 kHz 6
Data Hold Time tHD, DAT 0 900 ns 6
SDA and SCL Receiving Rise Time tR 300 ns Note 8: CB is in pF 6
SDA and SCL Receiving Fall Time tF 300 ns Note 8: CB is in pF 6
SDA Transmitting Fall Time tF 250 ns DVDD = 1.8V, TA = +25°C 6
Pulse Width of Suppressed Spike tSP 0 50 ns 6
Digital Supply Voltage (absolute) -0.3 4 V DVDD, AVDD, PVDD, voltages with respect to AGND 2
AVDD Referenced to PVDD -0.3 0.3 V 2
SVSS, PVSS -4 0.3 V 2
SVSS Referenced to PVSS -0.3 0.3 V 2
DGND, PGND -0.3 0.3 V 2
BCLK, LRCLK, HPS, SDIN -0.3 V Max = DVDD + 0.3V 2
GPIO, MCLK -0.3 4 V 2
REF, PREG -0.3 V Max = AVDD + 0.3V 2
SDA, SCL, ADD -0.3 4 V 2
INL, INR -2 2 V 2
Current Into/Out of Any Pin 100 mA Into or out of any pin 2
Junction Temperature 150 °C 2
Operating Temperature Range -40 85 °C 2
Storage Temperature Range -65 150 °C 2
Lead Temperature 300 °C Soldering, 10s 2

CAD (KiCad official)

  • Symbol: MAX9850ETI+T
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: TQFN-28(5x5) (KiCad packages3D, STEP)
  • 3D model files: max9850eti-t-etched.step / max9850eti-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max9850eti-t.step / max9850eti-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc./Maxim Integrated datasheet (36 pp, sha256 4e3255799108e3d5, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF