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MAX98091ETM+

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Maxim Integrated Audio Interface ICs, TQFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MAX98091ETM+

Maxim Integrated · Audio Interface ICs · TQFN-48(6x6)

MAX98091ETM+ from Maxim Integrated, in a TQFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C1N passive Charge-pump flying capacitor negative terminal; connect a 1µF ceramic capacitor between C1N and C1P.
2 HPGND power_in Headphone ground.
3 CPVSS power_out Inverting charge-pump output; bypass to HPGND with a 1µF ceramic capacitor.
4 CPVDD power_out Noninverting charge-pump output; bypass to HPGND with a 1µF ceramic capacitor.
5 HPL output Left-channel headphone output.
6 HPSNS input Headphone amplifier ground sense; connect to the headphone jack ground terminal or to ground.
7 HPR output Right-channel headphone output.
8 JACKSNS input Jack detection input; connect to the microphone terminal of the headset jack to detect jack activity.
9 RCVP/LOUTL output Positive earpiece amplifier output / left line output.
10 RCVN/LOUTR output Negative earpiece amplifier output / right line output.
11 SPKRGND power_in Right speaker amplifier ground.
12 SPKRN output Negative right-channel Class D speaker output.
13 SPKRP output Positive right-channel Class D speaker output.
14 SPKVDD power_in Speaker and microphone bias power supply; bypass each to SPK_GND with 1µF plus a single shared 10µF bulk capacitor.
15 SPKVDD power_in Speaker and microphone bias power supply; bypass each to SPK_GND with 1µF plus a single shared 10µF bulk capacitor.
16 N.C. unconnected No connection; not internally connected.
17 SPKLN output Negative left-channel Class D speaker output.
18 SPKLP output Positive left-channel Class D speaker output.
19 SPKLGND power_in Left speaker amplifier ground.
20 IN2/DMC1 input Negative differential microphone 1 input or single-ended line input 2; AC-couple with a series 1µF capacitor; can be retasked as digital microphone 1 clock output.
21 IN1/DMD1 input Positive differential microphone 1 input or single-ended line input 1; AC-couple with a series 1µF capacitor; can be retasked as digital microphone 1 data input.
22 N.C. unconnected No connection; not internally connected.
23 IN3 input Positive differential microphone 2 input or single-ended line input 3; AC-couple with a series 1µF capacitor.
24 N.C. unconnected No connection; not internally connected.
25 IN5/DMD2 input Auxiliary positive differential microphone input or single-ended line input; AC-couple with a series 1µF capacitor; can be retasked as digital microphone 2 data input.
26 IN4 input Negative differential microphone 2 input or single-ended line input 4; AC-couple with a series 1µF capacitor.
27 IN6/DMC2 input Auxiliary negative differential microphone input or single-ended line input; AC-couple with a series 1µF capacitor; can be retasked as digital microphone 2 clock output.
28 MICBIAS power_out Low-noise microphone bias voltage output; bypass to SPKLGND with 1µF; an external resistor in the 2.2kΩ to 1kΩ range sets the microphone current.
29 REF passive Converter reference; bypass to AGND with a 2.2µF capacitor.
30 BIAS passive Common-mode reference voltage; bypass to AGND with a 1µF capacitor.
31 AGND power_in Analog ground.
32 AVDD power_in Analog power supply; bypass to AGND with a 1µF capacitor.
33 N.C. unconnected No connection; not internally connected.
34 N.C. unconnected No connection; not internally connected.
35 N.C. unconnected No connection; not internally connected.
36 DVDD power_in Digital power supply; bypass to DGND with a 1µF capacitor.
37 DGND power_in Digital ground.
38 DVDDIO power_in Digital audio interface power supply input; bypass to DGND with a 1µF capacitor.
39 SDOUT output Digital audio serial-data ADC output; output voltage referenced to DVDDIO.
40 SDIN input Digital audio serial-data DAC input; input voltage referenced to DVDDIO.
41 LRCLK bidirectional Digital audio left-right clock; input in slave mode and output in master mode; referenced to DVDDIO.
42 BCLK bidirectional Digital audio bit clock; input in slave mode and output in master mode; referenced to DVDDIO.
43 IRQ output Active-low hardware interrupt output; connect a 10kΩ pullup resistor to VDD.
44 MCLK input Master clock input; acceptable input frequency range is 10MHz to 60MHz.
45 SCL input I2C serial-clock input; connect a pullup resistor to DVDD for full output swing.
46 SDA bidirectional I2C serial-data input/output; connect a pullup resistor to DVDD for full output swing.
47 HPVDD power_in Headphone power supply; bypass to HPGND with a 10µF bulk capacitor in parallel with a 0.1µF capacitor placed as close as possible to the device.
48 C1P passive Charge-pump flying capacitor positive terminal; connect a 1µF ceramic capacitor between C1N and C1P.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Maxim Integrated
Package TQFN-48(6x6)
Category Interface ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Range VSPKVDD 2.8 3.7 5.5 V Guaranteed by PSRR (Note 3) 11
Supply Voltage Range VAVDD, VHPVDD 1.65 1.8 2 V 11
Supply Voltage Range (TQFN) VDVDD 1.08 1.2 1.65 V TQFN package 11
Supply Voltage Range VDVDDIO 1.65 1.8 3.6 V 11
Operating Temperature Range -40 85 °C 11
Absolute Maximum Voltage AVDD, DVDD, HPVDD -0.3 2.2 V Voltages with respect to AGND 11
Absolute Maximum Voltage SPKVDD, DVDDIO -0.3 6 V Voltages with respect to AGND 11
Absolute Maximum Voltage DGND, HPGND, SPKLGND, SPKRGND -0.1 0.1 V Voltages with respect to AGND 11
Absolute Maximum Voltage MCLK, SDIN, SDA, SCL, IRQ -0.3 6 V Voltages with respect to AGND 11
Absolute Maximum Voltage IN1-IN6 -0.3 2.2 V Voltages with respect to AGND 11
Absolute Maximum Voltage JACKSNS -0.3 6 V Voltages with respect to AGND 11
Storage Temperature Range -65 150 °C 11
Shutdown Supply Current Analog IVDD 1 10 µA TA = +25°C 12
Shutdown Supply Current Speaker ISPKVDD 1 5 µA TA = +25°C 12
Shutdown Supply Current Digital IDVDD 2.1 5 µA TA = +25°C 12
Quiescent Supply Current Analog IVDD 1.45 2 mA DAC playback 48kHz stereo, headphone outputs 11
Quiescent Supply Current Digital IVDD 1.04 1.5 mA DAC playback 48kHz stereo, headphone outputs 11
MICBIAS Output Voltage VMICBIAS 2.1 2.2 2.29 V ILOAD = 1mA, MBVSEL[1:0] = 00 13
MICBIAS Output Voltage VMICBIAS 2.29 2.4 2.46 V ILOAD = 1mA, MBVSEL[1:0] = 01 13
MICBIAS Output Voltage VMICBIAS 2.46 2.57 2.69 V ILOAD = 1mA, MBVSEL[1:0] = 10 13
MICBIAS Output Voltage VMICBIAS 2.69 2.8 2.9 V ILOAD = 1mA, MBVSEL[1:0] = 11 13
Microphone Preamplifier Gain AV_MICPRE 19 20 21 dB PA_EN[1:0] = 10 13
Microphone Preamplifier Gain AV_MICPRE 29 30 31.25 dB PA_EN[1:0] = 11 13
Microphone Level Adjust Gain (PGA) AV_MICPGA 19 20 21 dB PGAM_[4:0] = 0x00 13
Line Input Level Adjust Gain (PGA) AV_LINEPGA 18 20 21.5 dB PGALIN = 0x0 14
Line Input Level Adjust Gain (PGA) AV_LINEPGA 13 14 15 dB PGALIN = 0x1 14
Input Resistance RIN 14 20 kΩ 14
Feedback Resistance RIN_FB 19 20 21 kΩ TA = +25°C 14
Receiver Volume Control (PGA) AV_RECPGA -63 -61 -59.5 dB RCVLVOL = 0x00 14
Receiver Volume Control (PGA) AV_RECPGA 7.2 8 8.75 dB RCVLVOL = 0x1F 14
Speaker Volume Control (PGA) AV_SPKPGA -51 -48 -44.5 dB SPVOLL/SPVOLR = 0x00 17
Speaker Volume Control (PGA) AV_SPKPGA 13 14 15 dB SPVOLL/SPVOLR = 0x1F 17
Headphone Volume Control (PGA) AV_HPPGA -68 -67 -65 dB HPVOL_ = 0x00 19
Headphone Volume Control (PGA) AV_HPPGA 2.25 3 3.5 dB HPVOL_ = 0x1F 19
Jack Sense High Threshold VTH_HIGH 0.8 0.95 0.98 x VMICBIAS MICBIAS enabled 20
Jack Sense Low Threshold VTH_LOW 0.06 0.1 0.17 x VMICBIAS MICBIAS enabled 20
Jack Sense High Threshold VTH_HIGH 0.8 0.95 0.98 x VSPKVDD MICBIAS disabled 20
Jack Sense Low Threshold VTH_LOW 0.06 0.1 0.17 x VSPKVDD MICBIAS disabled 20
JACKSNS Strong Pullup Resistance RSPU 1.9 2.4 2.7 kΩ MICBIAS disabled, JDWK = 0 20
JACKSNS Weak Pullup Current IWPU 5 12 µA MICBIAS disabled, JDWK = 1 20
MCLK Input Frequency fMCLK 10 60 MHz fS = 48kHz, music mode filters (MODE = 1) 27
MCLK Input Frequency fMCLK 2.048 60 MHz fS = 8kHz, voice mode filters (MODE = 0) 27
MCLK Input Frequency fMCLK 12.288 60 MHz fS = 96kHz, music mode filters (MODE = 1) 27
Serial Clock Frequency fSCL 0 400 kHz Guaranteed by SCL pulse width low and high 30
Bus Free Time Between STOP and START tBUF 1.3 µs 30
SCL Pulse-Width Low tLOW 1.3 µs 30
SCL Pulse-Width High tHIGH 0.6 µs 30
Hold Time (Repeated) START Condition tHD,STA 0.6 µs 30
Setup Time for a Repeated START Condition tSU,STA 0.6 µs 30
Data Setup Time tSU,DAT 100 ns 30
Setup Time for STOP Condition tSU,STO 0.6 µs 30
Pulse Width of Suppressed Spike tSP 0 50 ns 30
BCLK Cycle Time tBCLK 80 ns Slave mode 28
BCLK High Time tBCLKH 20 ns Slave mode 28
BCLK Low Time tBCLKL 20 ns Slave mode 28
Package Junction-to-Case Thermal Resistance θJC 1 °C/W TQFN 11

CAD (KiCad official)

  • Symbol: MAX98091ETM+
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: TQFN-48(6x6) (KiCad packages3D, STEP)
  • 3D model files: max98091etm-etched.step / max98091etm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max98091etm.step / max98091etm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Maxim Integrated datasheet (178 pp, sha256 5892bdd78a17bc0e, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF