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MAX9768BETG+T

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Analog Devices Inc Maxim Integrated Audio Amplifiers, TQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MAX9768BETG+T

Analog Devices Inc Maxim Integrated · Audio Amplifiers · TQFN-24(4x4)

MAX9768BETG+T from Analog Devices Inc Maxim Integrated, in a TQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT+ output Positive speaker output; the BTL speaker is driven differentially between OUT+ and OUT-.
2 OUT+ output Positive speaker output; the BTL speaker is driven differentially between OUT+ and OUT-.
3 PVDD power_in Speaker amplifier power-supply input, 4.5V to 14V; bypass with a 1µF capacitor to ground.
4 BOOT+ passive Positive speaker output boost flying-capacitor connection; connect a 0.1µF ceramic capacitor between BOOT+ and OUT+.
5 SCLK input I2C serial-clock input in I2C mode (ADDR1 and ADDR2 not GND); connect to VDD for classic PWM modulation or to ground for filterless modulation.
6 SDA/VOL bidirectional I2C serial data I/O and analog volume control input; the voltage applied sets the volume level in analog volume control mode.
7 FB input Feedback; connect the feedback resistor between FB and IN to set amplifier gain.
8 IN input Audio input.
9 GND power_in Ground; connect PGND and GND together at a single point on the PCB.
10 BIAS passive Common-mode bias voltage (1.5V typ); bypass with a 2.2µF capacitor to GND.
11 GND power_in Ground; connect PGND and GND together at a single point on the PCB.
12 SYNC input Frequency select and external clock input: GND selects 300kHz fixed, unconnected selects 360kHz fixed, VDD selects spread-spectrum 300kHz ±7.5kHz, and a clock input selects fixed-frequency sync to the external clock.
13 SYNCOUT output Clock signal output.
14 VDD power_in Power-supply input, 2.7V to 3.6V; bypass with a 1µF capacitor to GND.
15 BOOT- passive Negative speaker output boost flying-capacitor connection; connect a 0.1µF ceramic capacitor between BOOT- and OUT-.
16 PVDD power_in Speaker amplifier power-supply input, 4.5V to 14V; bypass with a 1µF capacitor to ground.
17 OUT- output Negative speaker output; the BTL speaker is driven differentially between OUT+ and OUT-.
18 OUT- output Negative speaker output; the BTL speaker is driven differentially between OUT+ and OUT-.
19 SHDN input Shutdown input; drive low to disable the audio amplifiers and connect to VDD for normal operation.
20 MUTE input Mute input; drive high to mute the speaker outputs and connect to GND for normal operation.
21 PGND power_in Power ground; connect PGND and GND together at a single point on the PCB.
22 PGND power_in Power ground; connect PGND and GND together at a single point on the PCB.
23 ADDR2 input Address select input 2; selects the I2C address option and also selects the volume control mode.
24 ADDR1 input Address select input 1; selects the I2C address option and also selects the volume control mode.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package TQFN-24(4x4)
Category Amplifiers/Comparators
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
PVDD to PGND PVDD -0.3 16 V 2
VDD to GND VDD -0.3 4 V 2
SCLK, SDA/VOL to GND -0.3 4 V 2
FB, SYNCOUT -0.3 V max printed as VDD + 0.3V 2
BOOT_ to OUT_ -0.3 4 V 2
OUT_ to GND -0.3 V max printed as PVDD + 0.3V 2
PGND to GND -0.3 0.3 V 2
Any other pin to GND -0.3 4 V 2
Continuous current (PVDD, PGND, OUT_) 2.2 A 2
Continuous input current (any other pin) -20 20 mA 2
Continuous input current (FB_) -60 60 mA 2
Storage temperature range -65 150 °C 2
Lead temperature 300 °C soldering, 10s 2
Operating temperature range -40 85 °C 2
Speaker supply voltage range PVDD 4.5 14 V Inferred from PSRR test 2
Supply voltage range VDD 2.7 3.6 V Inferred from PSRR and UVLO test 2
Quiescent current IVDD 7 14.2 mA 2
Quiescent current, filterless modulation IPVDD 4 7.6 mA Filterless modulation 2
Quiescent current, classic PWM modulation IPVDD 4 7.6 mA Classic PWM modulation 2
Shutdown current ISHDN 0.5 50 µA ISHDN = IPVDD + IDD, SHDN = GND, TA = +25°C 2
Output offset VOS -12.5 2 12.5 mV Filterless modulation, VMUTE = VDD, TA = +25°C 2
Output offset VOS -14 2 14 mV Filterless modulation, VMUTE = 0V, TA = +25°C 2
Input amplifier output voltage swing high VOH 3.6 100 mV Specified as VDD - VOH; RL = 2kΩ connect to 1.5V 2
Input amplifier output voltage swing low VOL 6 50 mV Specified as VOL - GND; RL = 2kΩ connect to 1.5V 2
Input amplifier output short-circuit current limit -60 60 mA 2
Internal gain AVMAX 29.27 30.1 31 dB Max volume setting; from FB to amplifier outputs /(OUT+) - (OUT-)/; excludes external gain resistors 2
Soft output current limit ILIM 1.75 2 A 3
Oscillator frequency fOSC 1060 1200 1320 kHz SYNC = GND 3
Oscillator frequency fOSC 1296 1440 1584 kHz SYNC = unconnected 3
Oscillator frequency, spread-spectrum fOSC -30 1200 30 kHz SYNC = VDD (spread-spectrum modulation mode); printed ±30 kHz 3
Class D switching frequency fSW 265 300 330 kHz SYNC = GND 4
Class D switching frequency fSW 324 360 396 kHz SYNC = unconnected 4
Class D switching frequency, spread-spectrum fSW -7.5 300 7.5 kHz SYNC = VDD (spread-spectrum modulation mode); printed ±7.5 kHz 4
SYNC frequency lock range 1000 1600 kHz 4
Minimum SYNC frequency lock duty cycle 40 % 4
Maximum SYNC frequency lock duty cycle 60 % 4
Input-voltage high, SYNC VIH 2.33 V SYNC 4
Input-voltage low, SYNC VIL 0.8 V SYNC 4
Input leakage current, SYNC ISYNC -13 7.5 13 µA TA = +25°C; printed ±7.5 typ, ±13 max 4
Input leakage current, all other digital inputs ILK -1 1 µA All other digital inputs, TA = +25°C 4
Output-voltage low, SYNCOUT 0.3 V Load = 1mA 4
Output-voltage low, SDA/VOL VOL 0.4 V IOL = 3mA 5
Output high current, SDA/VOL IOH 1 µA VOH = VDD 5
Input high leakage current IIH -1 1 µA VIN = VDD, TA = +25°C 5
Input low leakage current IIL -1 1 µA VIN = GND, TA = +25°C 5
Serial clock frequency fSCL 400 kHz I2C timing 5
Power-supply rejection ratio, PVDD PSRR 67 84 dB PVDD = 4.5V to 14V, filterless modulation, TA = +25°C 3
Power-supply rejection ratio, VDD PSRR 52 68 dB VDD = 2.7V to 3.6V, filterless modulation, TA = +25°C 3
Hard output current limit ISC 2.5 A 3
Thermal shutdown threshold 150 °C 5
Thermal shutdown hysteresis 15 °C 5
Input capacitance CIN 5 pF SCLK, SDA/VOL 5
Common-mode bias voltage VBIAS 1.5 V 2
Input amplifier gain-bandwidth product GBW 1.8 MHz 2
Turn-on time, MAX9768B tON 15 ms 2
Output power, PVDD = 14V POUT 10 W PVDD = 14V, RL = 8Ω, THD+N = 10%, filterless modulation 3

CAD (KiCad official)

  • Symbol: MAX9768BETG+T
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: TQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: max9768betg-t-etched.step / max9768betg-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max9768betg-t.step / max9768betg-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (23 pp, sha256 307be3f4b07b6dc8, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF