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MAX96724FGTN

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Analog Devices Inc./Maxim Integrated Serializers / Deserializers, TQFN-56(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MAX96724FGTN

Analog Devices Inc./Maxim Integrated · Serializers / Deserializers · TQFN-56(8x8)

MAX96724FGTN from Analog Devices Inc./Maxim Integrated, in a TQFN-56(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MFP0 bidirectional Multifunction pin 0 (FSYNC, LMN0 or GPIO0), disabled as high-impedance with a 1 MΩ pulldown at power-up.
2 MFP1 bidirectional Multifunction pin 1 (VSYNC0/DE0/HSYNC0, LMN1 or GPIO1), disabled as high-impedance at power-up.
3 MFP2 bidirectional Multifunction pin 2 (LMN2, GPIO2 or CNTL1/CNTL3 in GMSL1 mode), disabled as high-impedance at power-up.
4 CFG0 input Configuration input latched at power-up through an external resistor divider from VDDIO to set the I2C address and mode (Table 7).
5 SIODP bidirectional Noninverted GMSL2/GMSL1 serial-data I/O D.
6 SIODN bidirectional Inverted GMSL2/GMSL1 serial-data I/O D.
7 VDD18 power_in 1.8V analog supply, specified 1.7V to 1.9V.
8 CAP_VDD power_in Decoupling for the VDD core supply.
9 SIOCN bidirectional Inverted GMSL2/GMSL1 serial-data I/O C.
10 SIOCP bidirectional Noninverted GMSL2/GMSL1 serial-data I/O C.
11 PWDNB input Active-low power-down input with a 1 MΩ internal pulldown; set low to enter power-down and attach a pullup to VDDIO for normal operation.
12 MFP3 bidirectional Multifunction pin 3 (VSYNC1/DE1/HSYNC1, LMN3 or GPIO3), disabled as high-impedance at power-up.
13 MFP4 bidirectional Multifunction pin 4, LOCK output (open-drain with 40 kΩ pullup to VDDIO) by default, or GPIO4.
14 MFP5 bidirectional Multifunction pin 5, ERRB output (open-drain with 40 kΩ pullup to VDDIO) by default, or GPIO5.
15 X1/OSC input 25 MHz crystal or clock source input.
16 X2 passive Connect to the 25 MHz crystal; must be left floating when an external oscillator drives X1/OSC.
17 XRES passive Connect a 402 Ω 1% resistor to ground.
18 SIOBP bidirectional Noninverted GMSL2/GMSL1 serial-data I/O B.
19 SIOBN bidirectional Inverted GMSL2/GMSL1 serial-data I/O B.
20 CAP_VDD power_in Decoupling for the VDD core supply.
21 VDD18 power_in 1.8V analog supply, specified 1.7V to 1.9V.
22 SIOAN bidirectional Inverted GMSL2/GMSL1 serial-data I/O A.
23 SIOAP bidirectional Noninverted GMSL2/GMSL1 serial-data I/O A.
24 VDDIO power_in 3.3V or 1.8V I/O power supply, specified 1.7V to 3.6V.
25 CFG1/MFP6 bidirectional Configuration input CFG1 latched at power-up (Table 8), which becomes multifunction pin MFP6 (GPO6) after latching.
26 SDA1/MFP7 bidirectional I2C data 1, open-drain with 40 kΩ pullup to VDDIO, or alternate function/GPIO7.
27 SCL1/MFP8 bidirectional I2C clock 1, open-drain output with 40 kΩ pullup to VDDIO, or GPIO8.
28 SDA bidirectional I2C data, open-drain with 40 kΩ pullup to VDDIO.
29 SCL bidirectional I2C clock, open-drain with 40 kΩ pullup to VDDIO.
30 VTERM power_in 1.2V CSI C/D-PHY supply, specified 1.14V to 1.26V.
31 DA0P output D-PHY Port A data lane 0 positive output (4-lane mode), or C-PHY Port A lane 0 output A.
32 DA0N output D-PHY Port A data lane 0 negative output (4-lane mode), or C-PHY Port A lane 0 output B.
33 CKCP output D-PHY Port C clock lane positive output (2-lane mode); disabled in 4-lane mode.
34 CKCN output D-PHY Port C clock lane negative output (2-lane mode); disabled in 4-lane mode.
35 DA1P output D-PHY Port A data lane 1 positive output (4-lane mode), or C-PHY Port A lane 1 output B.
36 DA1N output D-PHY Port A data lane 1 negative output (4-lane mode), or C-PHY Port A lane 1 output C.
37 DA2P output D-PHY Port A data lane 2 positive output (4-lane mode), or C-PHY Port A lane 2 output A.
38 DA2N output D-PHY Port A data lane 2 negative output (4-lane mode), or C-PHY Port A lane 2 output B.
39 CKAP output D-PHY Port A clock lane positive output (4-lane mode).
40 CKAN output D-PHY Port A clock lane negative output (4-lane mode).
41 DA3P output D-PHY Port A data lane 3 positive output (4-lane mode), or C-PHY Port A lane 3 output B.
42 DA3N output D-PHY Port A data lane 3 negative output (4-lane mode), or C-PHY Port A lane 3 output C.
43 DB0P output D-PHY Port B data lane 0 positive output (4-lane mode), or C-PHY Port B lane 0 output A.
44 DB0N output D-PHY Port B data lane 0 negative output (4-lane mode), or C-PHY Port B lane 0 output B.
45 CKBP output D-PHY Port B clock lane positive output (4-lane mode).
46 CKBN output D-PHY Port B clock lane negative output (4-lane mode).
47 DB1P output D-PHY Port B data lane 1 positive output (4-lane mode), or C-PHY Port B lane 1 output B.
48 DB1N output D-PHY Port B data lane 1 negative output (4-lane mode), or C-PHY Port B lane 1 output C.
49 DB2P output D-PHY Port B data lane 2 positive output (4-lane mode), or C-PHY Port B lane 2 output A.
50 DB2N output D-PHY Port B data lane 2 negative output (4-lane mode), or C-PHY Port B lane 2 output B.
51 CKFP output D-PHY Port F clock lane positive output (2-lane mode); disabled in 4-lane mode.
52 CKFN output D-PHY Port F clock lane negative output (2-lane mode); disabled in 4-lane mode.
53 DB3P output D-PHY Port B data lane 3 positive output (4-lane mode), or C-PHY Port B lane 3 output B.
54 DB3N output D-PHY Port B data lane 3 negative output (4-lane mode), or C-PHY Port B lane 3 output C.
55 VDD power_in 1.2V or 1.0V core supply; 1.2V uses an internal regulator and 1.0V bypasses it.
56 VDD power_in 1.2V or 1.0V core supply; 1.2V uses an internal regulator and 1.0V bypasses it.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices Inc./Maxim Integrated
Package TQFN-56(8x8)
Category Communication Interface Chip/UART/485/232
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Voltage Swing (Single-ended) VO 190 250 310 mV RL = 100Ω ±1% 8
Output Voltage Swing (Differential) VODT 380 500 620 mV RL = 100Ω ±1%, peak-to-peak differential voltage 8
Change in VOD between Complementary Output States ΔVOD 25 mV RL = 100Ω ±1%, /VOD(H) − VOD(L)/ 8
Change in VOS between Complementary Output States ΔVOS 25 mV RL = 100Ω ±1%, /VOS(H) − VOS(L)/ 8
Termination Resistance (Internal), GMSL2 reverse channel RT 50 55 60 Ω Any Pin to VDD18 8
Termination Resistance (Internal), GMSL1 reverse channel RT 50 55 60 Ω Any Pin to VDD18 8
Differential High Output Peak Voltage, HIM disabled VRODH 30 70 mV Forward channel disabled, STP mode, RL=100Ω, HIM disabled 8
Differential High Output Peak Voltage, HIM enabled VRODH 50 110 mV Forward channel disabled, STP mode, RL=100Ω, HIM enabled 8
Differential Low Output Peak Voltage, HIM disabled VRODL -70 -30 mV Forward channel disabled, STP mode, RL=100Ω, HIM disabled 8
Differential Low Output Peak Voltage, HIM enabled VRODL -110 -50 mV Forward channel disabled, STP mode, RL=100Ω, HIM enabled 8
Thevenin High-Level Output Voltage (LP transmitter) VOH 0.95 1.2 1.3 V 8
Thevenin Low-Level Output Voltage (LP transmitter) VOL -50 50 mV 8
HS Transmit Static Common-Mode Voltage (D-PHY) VCMTX 150 200 250 mV 9
VCMTX Mismatch when Output is Differential-1 or Differential-0 (D-PHY) /ΔVCMTX(1, 0)/ 5 mV ∆VCMTX(1,0) = (VCMTX(1) - VCMTX(0)) / 2 9
HS Transmit Differential Voltage (D-PHY) /VOD/ 140 200 270 mV 9
VOD Mismatch when Output is Differential-1 or Differential-0 (D-PHY) /ΔVOD/ 14 mV 9
Single-Ended Output Impedance (D-PHY HS) ZOS 40 50 62.5 Ω 9
Single-Ended Output Impedance Mismatch (D-PHY HS) ∆ZOS 10 % 9
HS Transmit Static Common-Point Voltage (C-PHY) VCPTX 175 310 mV ZID = 100Ω 9
VCPTX Mismatch in any of the Six High-Speed States (C-PHY) /ΔVCPTX(HS)/ 9 mV (Figure 5) 9
Single-Ended Output Impedance (C-PHY HS) ZOS 40 50 60 Ω 9
Single-Ended Output Impedance Mismatch (C-PHY HS) ΔZOS 10 % 9
Low-Level Output Voltage (push-pull / open-drain outputs) VOL 0.4 V IOL = 4mA 10
Input Current (I/O pins) IIN 1 μA All pullup/pulldown devices disabled. VIN = 0V to VDDIO 10
Supply Current IDD1, GMSL2 mode, 3Gbps, VTERM IDD1 17 25 mA 4x 3Gbps input, 1x 4-lane D-PHY 2500Mbps/lane; VTERM = 1.26V 11
Supply Current IDD1, GMSL2 mode, 3Gbps, VDD18 IDD1 280 325 mA 4x 3Gbps input, 1x 4-lane D-PHY 2500Mbps/lane; VDD18 = 1.9V 11
Supply Current IDD1, GMSL2 mode, 3Gbps, VDD IDD1 197 625 mA 4x 3Gbps input, 1x 4-lane D-PHY 2500Mbps/lane; VDD = 1.05V 11
Supply Current IDD1, GMSL2 mode, 3Gbps, VDD high IDD1 191 600 mA 4x 3Gbps input, 1x 4-lane D-PHY 2500Mbps/lane; VDD = 1.26V 11
Supply Current IDD1, GMSL2 mode, 6Gbps, VTERM IDD1 19 35 mA 4x 6Gbps input, 1x 4-lane C-PHY 5700Mbps/lane (MAX96724); VTERM = 1.26V 11
Supply Current IDD1, GMSL2 mode, 6Gbps, VDD18 IDD1 280 325 mA 4x 6Gbps input, 1x 4-lane C-PHY 5700Mbps/lane (MAX96724); VDD18 = 1.9V 11
Supply Current IDD1, GMSL2 mode, 6Gbps, VDD 1.05V IDD1 244 675 mA 4x 6Gbps input, 1x 4-lane C-PHY 5700Mbps/lane (MAX96724); VDD = 1.05V 11
Supply Current IDD1, GMSL2 mode, 6Gbps, VDD 1.26V IDD1 228 650 mA 4x 6Gbps input, 1x 4-lane C-PHY 5700Mbps/lane (MAX96724); VDD = 1.26V 11
Supply Current IDD1, GMSL1 mode, VTERM IDD1 16 25 mA 4x 3.12Gbps input, 1x 4-lane D-PHY 2500Mbps/lane; VTERM = 1.2V 12
Supply Current IDD1, GMSL1 mode, VDD18 IDD1 155 200 mA 4x 3.12Gbps input, 1x 4-lane D-PHY 2500Mbps/lane; VDD18 = 1.8V 12
Supply Current IDD1, GMSL1 mode, VDD 1.05V IDD1 113 550 mA 4x 3.12Gbps input, 1x 4-lane D-PHY 2500Mbps/lane; VDD = 1.05V 12
Supply Current IDD1, GMSL1 mode, VDD 1.26V IDD1 107 525 mA 4x 3.12Gbps input, 1x 4-lane D-PHY 2500Mbps/lane; VDD = 1.26V 12
GMSL Reverse Channel Transmitter Rise/Fall Time tR, tF 2300 ps 20% to 80%, VO = 250mV, RL = 100Ω 12
Reference Clock Frequency Stability + Frequency Tolerance (crystal) fTN -200 200 ppm Crystal, 25 MHz 17
Reference Clock Duty Cycle (external input) DC 40 50 60 % 17
Supply Range VTERM VTERM 1.14 1.2 1.26 V 25
Supply Range VDD18 VDD18 1.7 1.8 1.9 V 25
Supply Range VDD (nominal 1.0V) VDD 0.95 1 1.05 V Nominal 1.0V 25
Supply Range VDD (nominal 1.2V) VDD 1.14 1.2 1.26 V Nominal 1.2V 25
Supply Range VDDIO VDDIO 1.7 3.6 V 25
Operating Junction Temperature (TJ) TJ -40 125 ºC 25
Absolute Maximum VDDIO VDDIO -0.3 3.9 V All voltages with respect to ground 7
Absolute Maximum VDD18 VDD18 -0.3 2 V All voltages with respect to ground 7
Absolute Maximum VDD VDD -0.3 2 V All voltages with respect to ground 7
Absolute Maximum VTERM VTERM -0.3 1.32 V All voltages with respect to ground 7
Absolute Maximum CAP_VDD CAP_VDD -0.3 1.2 V All voltages with respect to ground 7
Storage Temperature Range -40 150 °C 7
Soldering Temperature (reflow) 260 °C 7
Thermal Resistance Junction to Ambient (θJA), 56-pin TQFN-SW θJA 25 Four-layer board, JESD51-7 7
Thermal Resistance Junction to Case (θJC), 56-pin TQFN-SW θJC 4 Four-layer board, JESD51-7 7

CAD (KiCad official)

  • Symbol: MAX96724FGTN
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: TQFN-56(8x8) (KiCad packages3D, STEP)
  • 3D model files: max96724fgtn-etched.step / max96724fgtn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max96724fgtn.step / max96724fgtn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc./Maxim Integrated datasheet (474 pp, sha256 3182d34d76afe981, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF