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MAX96714GTJ
Public Made by Adomby adom
Analog Devices Inc./Maxim Integrated Serializers, Deserializers, TQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMAX96714GTJ
Analog Devices Inc./Maxim Integrated · Serializers, Deserializers · TQFN-32-EP(5x5)
MAX96714GTJ from Analog Devices Inc./Maxim Integrated, in a TQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MFP0 | bidirectional | Multifunction pin (VS, DE/DV, MS, FSYNC_OUT, or GPIO0) whose power-up default is GPI0 with a 1MΩ pulldown to ground. |
| 2 | MFP1 | bidirectional | Multifunction pin carrying pass-through I2C SDA1 or UART RX1 (open-drain with 40kΩ pullup to VDDIO, 1Mbps default UART rate), or GPIO1. |
| 3 | MFP2 | bidirectional | Multifunction pin carrying pass-through I2C SCL1 or UART TX1 (open-drain with 40kΩ pullup to VDDIO), or MS, FSYNC_OUT, or GPIO2. |
| 4 | MFP3 | bidirectional | Primary I2C SDA (open-drain output with 40kΩ pullup to VDDIO) or UART RX, selected by the CFG0 state at power-up. |
| 5 | CFG0 | input | Configuration input whose voltage is latched at power-up through an external resistor divider to set the device address and I2C/UART select per Table 8. |
| 6 | MFP4 | bidirectional | Primary I2C SCL (open-drain output with 40kΩ pullup to VDDIO) or UART TX, selected by the CFG0 state at power-up. |
| 7 | MFP5 | bidirectional | Open-drain LOCK output with 40kΩ pullup to VDDIO, alternately programmable as VS, DE/DV push-pull monitor output, or GPIO5. |
| 8 | X1/OSC | input | Crystal or oscillator input for a 25MHz crystal (±200ppm per Table 2); if an oscillator is used, connect it to this pin. |
| 9 | X2 | passive | Second crystal terminal for the 25MHz crystal; leave floating if an oscillator drives X1. |
| 10 | XRES | passive | Connect a 402Ω ±1% resistor between XRES and ground. |
| 11 | VDD18 | power_in | 1.8V analog supply (Table 1 range 1.7V to 1.9V). |
| 12 | SION/SIO | bidirectional | Inverted GMSL serial-data input/output (SION for twisted pair, SIO for coax), with the mode set by the CFG1 state at power-up. |
| 13 | SIOP | bidirectional | Noninverted GMSL serial-data input/output for twisted pair; in coax mode this unused input is terminated with RTERM (49.9Ω) next to its link isolation capacitor. |
| 14 | CAP_VDD | passive | Decoupling capacitor connection for the 1.0V core supply; place a 10nF capacitor as close as possible to the pin with at least 10µF bulk nearby. |
| 15 | VDD | power_in | 1.0V core supply: connect 0.95V to 1.05V to bypass the internal LDO, or 1.14V to 1.26V to use the internal 1.0V regulator (after writing REG_ENABLE=1 and LDO_TEST=1). |
| 16 | CFG1 | input | Configuration input whose voltage is latched at power-up through an external resistor divider to set the link and mode options per Table 9. |
| 17 | VDDIO | power_in | 1.8V to 3.3V I/O supply (Table 1 gives 1.7V to 3.6V). |
| 18 | MFP6 | bidirectional | Line-fault monitor input LMN0, or GPIO6 (power-up default GPI6 with 1MΩ pulldown to ground), or CNTL2 push-pull output in GMSL1 mode. |
| 19 | MFP7 | bidirectional | Line-fault monitor input LMN1, or GPIO7 (power-up default GPI7 with 1MΩ pulldown to ground), or CNTL0 push-pull output in GMSL1 mode. |
| 20 | VTERM | power_in | 1.2V D-PHY supply (Table 1 range 1.14V to 1.26V). |
| 21 | D0P | output | MIPI D-PHY data lane 0 noninverted output, supporting up to 2.5Gbps per lane. |
| 22 | D0N | output | MIPI D-PHY data lane 0 inverted output, supporting up to 2.5Gbps per lane. |
| 23 | D1P | output | MIPI D-PHY data lane 1 noninverted output, supporting up to 2.5Gbps per lane. |
| 24 | D1N | output | MIPI D-PHY data lane 1 inverted output, supporting up to 2.5Gbps per lane. |
| 25 | D2P | output | MIPI D-PHY data lane 2 noninverted output, supporting up to 2.5Gbps per lane. |
| 26 | D2N | output | MIPI D-PHY data lane 2 inverted output, supporting up to 2.5Gbps per lane. |
| 27 | CKP | output | MIPI D-PHY clock lane noninverted output, supporting up to 2.5Gbps per lane. |
| 28 | CKN | output | MIPI D-PHY clock lane inverted output, supporting up to 2.5Gbps per lane. |
| 29 | D3P | output | MIPI D-PHY data lane 3 noninverted output, supporting up to 2.5Gbps per lane. |
| 30 | D3N | output | MIPI D-PHY data lane 3 inverted output, supporting up to 2.5Gbps per lane. |
| 31 | PWDNB | input | Active-low power-down input with a 1MΩ pulldown to ground; driving it low places the device in power-down mode. |
| 32 | MFP8 | bidirectional | Open-drain ERRB error output with 40kΩ pullup to VDDIO that goes low when an error is detected, or GPIO8. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc./Maxim Integrated |
| Package | TQFN-32-EP(5x5) |
| Category | Interface |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Range VTERM (D-PHY termination supply) | VTERM | 1.14 | 1.2 | 1.26 | V | Nominal 1.2 V | 22 |
| Supply Range VDD18 (primary analog supply) | VDD18 | 1.7 | 1.8 | 1.9 | V | 22 | |
| Supply Range VDD (core, 1.0V mode) | VDD | 0.95 | 1 | 1.05 | V | Nominal 1.0 V | 22 |
| Supply Range VDD (core, 1.2V mode) | VDD | 1.14 | 1.2 | 1.26 | V | Nominal 1.2 V | 22 |
| Supply Range VDDIO (GPIO supply) | VDDIO | 1.7 | 3.6 | V | 22 | ||
| Operating Junction Temperature (TJ) | TJ | -40 | 125 | °C | 22 | ||
| VDDIO absolute maximum (all voltages with respect to ground) | VDDIO | -0.3 | 3.9 | V | 6 | ||
| VDD18 absolute maximum | VDD18 | -0.3 | 2 | V | 6 | ||
| VDD absolute maximum | VDD | -0.3 | 2 | V | 6 | ||
| VTERM absolute maximum | VTERM | -0.3 | 1.32 | V | 6 | ||
| CAP_VDD absolute maximum | CAP_VDD | -0.3 | 1.2 | V | 6 | ||
| SIO_ absolute maximum (inactive state) | SIO_ | -0.3 | 1.1 | V | Inactive state (Note 1) | 6 | |
| Storage Temperature Range | TSTG | -40 | 150 | °C | 6 | ||
| Soldering Temperature (Reflow) | 260 | °C | 6 | ||||
| Output Voltage Swing (Single-Ended), GMSL2 reverse channel | VO | 190 | 250 | 310 | mV | RL = 100Ω ±1% | 7 |
| Output Voltage Swing (Differential), GMSL2 reverse channel | VODT | 380 | 500 | 620 | mV | RL = 100Ω ±1%, peak-to-peak differential voltage | 7 |
| Change in VOD between Complementary Output States | ΔVOD | 25 | mV | RL = 100Ω ±1%, /VOD(H) − VOD(L)/ | 7 | ||
| Change in VOS between Complementary Output States | ΔVOS | 25 | mV | RL = 100Ω ±1%, /VOS(H) − VOS(L)/ | 7 | ||
| Termination Resistance (Internal), GMSL2 reverse channel | RT | 50 | 55 | 60 | Ω | Any pin to VDD18 | 7 |
| Differential High Output Peak Voltage, GMSL1 (HIM disabled) | VRODH | 30 | 75 | mV | Forward channel disabled. See Figure 2. HIM disabled. | 7 | |
| Differential High Output Peak Voltage, GMSL1 (HIM enabled) | VRODH | 50 | 120 | mV | Forward channel disabled. See Figure 2. HIM enabled. | 7 | |
| Differential Low Output Peak Voltage, GMSL1 (HIM disabled) | VRODL | -75 | -30 | mV | Forward channel disabled. See Figure 2. HIM disabled. | 7 | |
| Differential Low Output Peak Voltage, GMSL1 (HIM enabled) | VRODL | -120 | -50 | mV | Forward channel disabled. See Figure 2. HIM enabled. | 7 | |
| Single-Ended High-Output Peak Voltage, GMSL1 (HIM disabled) | VROSH | 30 | 75 | mV | Forward channel disabled. HIM disabled. | 7 | |
| Single-Ended High-Output Peak Voltage, GMSL1 (HIM enabled) | VROSH | 50 | 120 | mV | Forward channel disabled. HIM enabled. | 7 | |
| Single-Ended Low-Output Peak Voltage, GMSL1 (HIM disabled) | VROSL | -75 | -30 | mV | Forward channel disabled. HIM disabled. | 7 | |
| Single-Ended Low-Output Peak Voltage, GMSL1 (HIM enabled) | VROSL | -120 | -50 | mV | Forward channel disabled. HIM enabled. | 7 | |
| Termination Resistance (Internal), GMSL1 reverse channel | RT | 50 | 55 | 60 | Ω | Any pin to VDD18 | 7 |
| D-PHY LP Transmitter High-Level Output Voltage | VOH | 0.95 | 1.2 | 1.3 | V | 7 | |
| D-PHY LP Transmitter Low-Level Output Voltage | VOL | -50 | 50 | mV | 7 | ||
| HS Transmit Static Common-Mode Voltage | VCMTX | 150 | 200 | 250 | mV | See Figure 3. | 7 |
| VCMTX Mismatch When Output is Differential-1 or Differential-0 | /ΔVCMTX(1,0)/ | 5 | mV | ΔVCMTX(1,0) = (VCMTX(1) − VCMTX(0))/2. See Figure 4. | 7 | ||
| HS Transmit Differential Voltage | /VOD/ | 140 | 200 | 270 | mV | See Figure 3. | 7 |
| VOD Mismatch When Output is Differential-1 or Differential-0 | /ΔVOD/ | 14 | mV | See Figure 4. | 8 | ||
| HS Output High Voltage | VOHHS | 360 | mV | 8 | |||
| Single-Ended Output Impedance (HS) | ZOS | 40 | 50 | 62.5 | Ω | 8 | |
| Single-Ended Output Impedance Mismatch (HS) | ΔZOS | 15 | % | 8 | |||
| Low-Level Output Voltage (open-drain pins) | VOL | 0.4 | V | IOL = 4mA | 8 | ||
| Input Current (I/O pins) | IIN | 1 | μA | All pullup/pulldown devices disabled. VIN = 0V to VDDIO | 8 | ||
| Low-Level Output Voltage (push-pull outputs) | VOL | 0.4 | V | IOL = 4mA | 9 | ||
| Input Current (PWDNB pin) | IIN | 6 | μA | VIN = 0V to VDDIO | 9 | ||
| Supply Current IDD, GMSL2 6Gbps (MAX96714), VDD = 1.0V | IDD | 120 | 260 | mA | 6Gbps link, 5.2Gbps video payload, PRBS24, four data lanes, 1.3Gbps per lane | 9 | |
| Supply Current IDD, GMSL2 6Gbps (MAX96714), VDD = 1.2V | IDD | 124 | 250 | mA | 6Gbps link, 5.2Gbps video payload, PRBS24, four data lanes, 1.3Gbps per lane | 9 | |
| Supply Current IDD, GMSL2 6Gbps (MAX96714), VDD18 = 1.8V | IDD | 115 | 158 | mA | 6Gbps link, 5.2Gbps video payload, PRBS24, four data lanes, 1.3Gbps per lane | 9 | |
| Supply Current IDD, GMSL2 6Gbps (MAX96714), VTERM = 1.2V | IDD | 14 | 25 | mA | 6Gbps link, 5.2Gbps video payload, PRBS24, four data lanes, 1.3Gbps per lane | 9 | |
| Maximum VDDIO Supply Current | IDDIO | 44 | μA/MHz | Per toggling GPIO, CL = 20pF, VDDIO at 1.9V | 9 | ||
| Maximum VDDIO Supply Current | IDDIO | 81 | μA/MHz | Per toggling GPIO, CL = 20pF, VDDIO at 3.6V | 9 | ||
| Lock Time (GMSL2, MAX96714/MAX96714F) | tLOCK2 | 31 | ms | From power-up, one-shot reset, or rising edge of PWDNB to rising edge of LOCK (Note 9) | 10 | ||
| PWDNB Hold Time | tHOLD_PWDNB | 1 | ms | Minimum duration PWDNB must be held LOW to reset the chip | 10 | ||
| Maximum Lock Time, GMSL1 | tLOCK1 | 4 | ms | See Figure 6. | 11 | ||
| Data Bit Rate, D-PHY | DLBR | 80 | 2500 | Mbps | 11 | ||
| Clock Lane Frequency, D-PHY | CLFREQ | 40 | 1250 | MHz | 11 | ||
| UI Instantaneous, D-PHY data-clock timing | UIINST | 0.4 | 12.5 | ns | 11 | ||
| Maximum Power-Down Current (VDDIO) | IDD | 6 | μA | VDDIO at 3.6V, TA = 105°C | 10 | ||
| Maximum Power-Down Current (VDD18) | IDD | 10 | μA | VDD18 at 1.9V, TA = 105°C | 10 | ||
| Output Fall Time (I2C/UART port, MAX96714/MAX96714F) | tF | 150 | ns | 70% to 30%, CL = 20pF to 100pF, 1kΩ pullup to VDDIO | 13 | ||
| I2C/UART Wake Time (MAX96714/MAX96714F) | tWAKEUP | 12.25 | ms | From power-up, or rising edge of PWDNB to local register access | 13 | ||
| Junction to Ambient Thermal Resistance (TQFN-SW-EP, four-layer board) | θJA | 29 | °C/W | Four-layer board, still air, JEDEC JESD51-7 | 6 | ||
| Junction to Case Thermal Resistance (TQFN-SW-EP) | θJC | 1.7 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
MAX96714GTJ - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: TQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
max96714gtj-etched.step/max96714gtj-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);max96714gtj.step/max96714gtj.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices Inc./Maxim Integrated datasheet (210 pp, sha256
f57e4f6aee81b7ee, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).