component
MAX745EAP+T
Public Made by Adomby adom
Analog Devices Inc Maxim Integrated Battery Management, SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MAX745EAP+T
Analog Devices Inc Maxim Integrated · Battery Management · SSOP-20-208mil
MAX745EAP+T from Analog Devices Inc Maxim Integrated, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IBAT | output | Current-sense amplifier's analog current-source output, which sources a current of 0.9µA/mV times the current-sense voltage and should be tied to GND through a scaling resistor or to GND if unused. |
| 2 | DCIN | power_in | Charger input voltage, specified at 6V to 24V, to be bypassed with a 0.1µF capacitor. |
| 3 | VL | power_out | Output of the internal 5.4V linear regulator from DCIN that powers the chip, to be bypassed with a 4.7µF capacitor. |
| 4 | CCV | passive | Voltage-regulation-loop compensation point. |
| 5 | CCI | passive | Current-regulation-loop compensation point. |
| 6 | THM/SHDN | input | Thermistor sense-voltage input that also serves as shutdown, turning the charger off when pulled low (rising threshold 2.20V to 2.34V, falling threshold 2.01V to 2.19V). |
| 7 | REF | power_out | 4.2V reference voltage output that must be bypassed with a 0.1µF or greater capacitor. |
| 8 | VADJ | input | Voltage-adjustment input tied to a 1% resistor divider to set the voltage set point by 10%, with an input range of 0V to VREF. |
| 9 | SETI | input | Charging-current set input, tied to a resistor divider between REF and GND, with an input range of 0V to VREF. |
| 10 | GND | power_in | Analog ground. |
| 11 | CELL1 | input | Logic input for cell-count selection per Table 1 (CELL0/CELL1 = GND/GND selects 1 cell, VL/GND 2, GND/VL 3, VL/VL 4). |
| 12 | CELL0 | input | Logic input for cell-count selection per Table 1 (CELL0/CELL1 = GND/GND selects 1 cell, VL/GND 2, GND/VL 3, VL/VL 4). |
| 13 | STATUS | output | Open-drain output that sinks current in current-regulation mode and is high impedance in voltage-regulation mode, to be pulled up to VL through 1kΩ to 100kΩ or left floating if unused. |
| 14 | BATT | input | Battery-voltage sense input and current-sense negative input, with an absolute maximum of 20V to GND. |
| 15 | CS | input | Current-sense positive input, used with BATT across the current-sense resistor, with an absolute maximum of 20V to GND. |
| 16 | PGND | power_in | Power ground for the external MOSFET drivers, which must be within 0.3V of GND. |
| 17 | DLO | output | Low-side power MOSFET gate driver output. |
| 18 | DHI | output | High-side power MOSFET gate driver output, referenced to LX and driven from BST. |
| 19 | LX | passive | Power connection for the high-side power MOSFET source. |
| 20 | BST | power_in | Power input for the high-side MOSFET driver, which charges through the bootstrap diode and capacitor to above the input voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | SSOP-20-208mil |
| Category | Power Management (PMIC) |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DCIN to GND | -0.3 | 26 | V | 2 | |||
| BST, DHI to GND | -0.3 | 30 | V | 2 | |||
| BST to LX | -0.3 | 6 | V | 2 | |||
| VL to GND | -0.3 | 6 | V | 2 | |||
| BATT, CS to GND | -0.3 | 20 | V | 2 | |||
| PGND to GND | -0.3 | 0.3 | V | 2 | |||
| Operating Temperature Range | -40 | 85 | °C | 2 | |||
| Storage Temperature | -60 | 150 | °C | 2 | |||
| Lead Temperature (soldering) | 300 | °C | soldering, 10s | 2 | |||
| DCIN Input Voltage Range | 6 | 24 | V | 2 | |||
| REF Output Voltage | 4.14 | 4.26 | V | 6.0V < VDCIN < 24V | 3 | ||
| VL Output Voltage | 5.1 | 5.7 | V | 6.0V < VDCIN < 24V, no load | 3 | ||
| Oscillator Frequency | 260 | 340 | kHz | 3 | |||
| DHI Maximum Duty Cycle | 89 | 93 | % | 2 | |||
| DHI On-Resistance | 7 | Ω | Output high or low | 3 | |||
| DLO On-Resistance | 14 | Ω | Output high or low | 3 | |||
| CS to BATT Full-Scale Current-Sense Voltage | 165 | 205 | mV | 3 | |||
| CS to BATT Current-Sense Voltage | 14 | 18 | 22 | mV | SETI = 400mV | 2 | |
| CS to BATT Offset Voltage | -1.5 | 1.5 | mV | 2 | |||
| Absolute Voltage Accuracy | -1 | 1 | % | Not including VADJ resistors | 3 | ||
| Absolute Voltage Accuracy | -0.75 | 0.75 | % | With 1% tolerance VADJ resistors | 2 | ||
| REF Output Load Regulation | 10 | 20 | mV/mA | 0 < IREF < 1mA | 2 | ||
| BATT, CS Input Voltage Range | 0 | 19 | V | 4V < VBATT < 16V | 2 | ||
| GMV Amplifier Output Current | -130 | 130 | µA | 3 | |||
| GMI Amplifier Output Current | -320 | 320 | µA | 3 | |||
| CCI Clamp Voltage with Respect to CCV | 25 | 80 | 200 | mV | 1.1V < VCCV < 3.5V | 3 | |
| CCV Clamp Voltage with Respect to CCI | 25 | 80 | 200 | mV | 1.1V < VCCI < 3.5V | 3 | |
| CELL0, CELL1 Input Bias Current | -1 | 1 | µA | 3 | |||
| SETI, VADJ Input Bias Current | -10 | 10 | nA | 3 | |||
| SETI Input Voltage Range | 0 | V | 3 | ||||
| VADJ Input Voltage Range | 0 | V | 3 | ||||
| THM/SHDN Rising Threshold | 2.2 | 2.3 | 2.34 | V | 3 | ||
| THM/SHDN Falling Threshold | 2.01 | 2.1 | 2.19 | V | 3 | ||
| IBAT Compliance Voltage Range | 0 | 2 | V | 3 | |||
| GMV Amplifier Transconductance | 800 | µA/V | 3 | ||||
| GMI Amplifier Transconductance | 200 | µA/V | 3 | ||||
| VADJ Adjustment Range | 10 | % | 3 | ||||
| DCIN Quiescent Supply Current | 4 | 6 | mA | 6.0V < VDCIN < 24V, logic inputs = VL | 2 | ||
| BATT Input Current | 5 | µA | VL < 3.2V, VBATT = 12V | 2 | |||
| BATT Input Current | 500 | µA | VL > 5.15V, VBATT = 12V | 2 | |||
| CS Input Current | 5 | µA | VL < 3.2V, VCS = 12V | 2 | |||
| CS Input Current | 400 | µA | VL > 5.15V, VCS = 12V | 2 | |||
| STATUS Output Low Voltage | 0.2 | V | Charger in current-regulation mode, STATUS sinking 1mA | 3 | |||
| STATUS Output Leakage Current | 1 | µA | Charger in voltage-regulation mode, VSTATUS = 5V | 3 | |||
| IBAT Output Current vs. Current-Sense Voltage | 0.9 | µA/mV | VIBAT = 2V | 3 | |||
| Continuous Power Derating (SSOP) | 8 | mW/°C | above +70°C | 2 |
CAD (KiCad official)
- Symbol:
MAX745EAP+T - Footprint:
Package_SO:SSOP-20_5.3x7.2mm_P0.65mm - 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
- 3D model files:
max745eap-t-etched.step/max745eap-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);max745eap-t.step/max745eap-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices Inc Maxim Integrated datasheet (9 pp, sha256
4c84dfcbbff35d8c, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).