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MAX6756UKTD3+T

Maxim Integrated · Monitors & Reset Circuits · SOT-23-5

MAX6756UKTD3+T from Maxim Integrated, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Power voltage input that powers the device and is the monitored voltage, operating from 1.0V to 6.0V; a 100Ω resistor in series with a 0.1µF bypass capacitor (RC filter) is recommended for the MAX6756 to ensure proper operation during extreme transition events.
2 GND power_in Ground reference for the device; all voltages in the datasheet are referenced to GND.
3 MR input Active-low manual reset input that asserts the reset outputs when driven low, with a minimum pulse width of 4µs and an internal 26kΩ pullup to VCC.
4 RESET output Active-low open-drain reset output that asserts when VCC is below the UVTH threshold or above the OVTH threshold and deasserts after the specified timeout period (100ms min, 185ms typ for the D3 option).
5 SET input Threshold window select input that sets the window to ±5% when connected to GND, ±10% when connected to VCC, and ±15% when biased to VCC/2.

Key specifications

Parameter Value
Manufacturer Maxim Integrated
Package SOT-23-5
Category Power Management ICs
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Voltage Range VCC 1 6 V TA = -40°C to +125°C 3
VCC Supply Current ICC 13 30 µA VCC = 3.6V, MAX6754-MAX6759, no load 3
VCC Overvoltage Threshold 3.3V (VSET=VSB) OVTH 3.795 3.878 3.96 V TA = -40°C to +125°C, rising VCC, VSET = VSB 3
VCC Overvoltage Threshold 3.3V (SET=VCC) OVTH 3.63 3.713 3.795 V TA = -40°C to +125°C, rising VCC, SET = VCC 3
VCC Overvoltage Threshold 3.3V (SET=GND) OVTH 3.465 3.548 3.63 V TA = -40°C to +125°C, rising VCC, SET = GND 3
VCC Undervoltage Threshold 3.3V (VSET=VSB) UVTH 2.64 2.723 2.805 V TA = -40°C to +125°C, falling VCC, VSET = VSB 4
VCC Undervoltage Threshold 3.3V (SET=VCC) UVTH 2.805 2.888 2.97 V TA = -40°C to +125°C, falling VCC, SET = VCC 4
VCC Undervoltage Threshold 3.3V (SET=GND) UVTH 2.97 3.053 3.135 V TA = -40°C to +125°C, falling VCC, SET = GND 4
Threshold Hysteresis VHYST 0.7 % VCC, VCC2 5
Reset and UV Timeout Period (D3) tRP 100 185 320 ms Figure 7, D3 option 6
VCC to Reset Delay tD-RESET 20 µs VCC falling at 10mV/µs from UVTH + 100mV to UVTH - 100mV 6
VCC to UV Delay tD-UV 20 µs VCC rising at 10mV/µs from OVTH - 100mV to OVTH + 100mV 6
Input-Voltage Low (SET) 0 0.1 V SET pin 6
Input Current (SET) ISET -1 1 µA 6
Manual Reset Pullup Resistance to VCC 26 kΩ MR pin, internal pullup 6
Manual Reset Minimum Pulse Width 4 µs MR pin 6
RESET Output Low (Open Drain) at 1.0V VOL 0.3 V Any VCC ≥ 1.0V, ISINK = 100µA, output asserted 7
RESET Output Low (Open Drain) at 1.2V VOL 0.3 V Any VCC ≥ 1.2V, ISINK = 200µA, output asserted 7
RESET Output Low (Open Drain) at 1.71V VOL 0.3 V Any VCC ≥ 1.71V, ISINK = 1.0mA, output asserted 7
RESET Output Low (Open Drain) at 2.85V VOL 0.3 V Any VCC ≥ 2.85V, ISINK = 2.0mA, output asserted 7
RESET Output Low (Open Drain) at 4.75V VOL 0.3 V Any VCC ≥ 4.75V, ISINK = 4.0mA, output asserted 7
RESET Output Open-Drain Leakage Current ILKG 1 µA Output not asserted 8
Voltage on VCC (to GND) VCC -0.3 6.5 V Voltages with respect to GND 2
Voltage on SET, MR (to GND) SET, MR -0.3 V Voltages with respect to GND, upper limit VCC + 0.3V 2
Voltage on RESET (open drain) (to GND) RESET -0.3 6.5 V Open-drain output, voltages with respect to GND 2
Input/Output Current (all pins) 20 mA All pins 2
Continuous Power Dissipation (5-Pin SOT23-5) 312 mW TA = +70°C, derate 3.9mW/°C above TA = +70°C 2
Operating Temperature Range TA -40 125 °C 2
Junction Temperature TJ 150 °C 2
Storage Temperature Range TSTG -65 150 °C 2
Lead Temperature (soldering, 10s) 300 °C Soldering, 10s 2
Soldering Temperature (reflow), Lead(Pb)-Free Package 260 °C Reflow, lead-free package 2
Thermal Resistance Junction to Ambient, Single-Layer Board (5-pin SOT23) θJA 324.3 °C/W Single-layer board 2
Thermal Resistance Junction to Case, Single-Layer Board (5-pin SOT23) θJC 82 °C/W Single-layer board 2
Thermal Resistance Junction to Ambient, Multi-Layer Board (5-pin SOT23) θJA 255.9 °C/W Multi-layer board 2
Thermal Resistance Junction to Case, Multi-Layer Board (5-pin SOT23) θJC 81 °C/W Multi-layer board 2

CAD (KiCad official)

  • Symbol: MAX6756UKTD3+T
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: max6756uktd3-t-etched.step / max6756uktd3-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max6756uktd3-t.step / max6756uktd3-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Maxim Integrated datasheet (19 pp, sha256 358b124e18e78fb9, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF