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MAX5974AETE+T

Analog Devices Inc Maxim Integrated · Battery Management · TQFN-16-EP(3x3)

MAX5974AETE+T from Analog Devices Inc Maxim Integrated, in a TQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DT passive Dead-time programming resistor connection; resistor RDT from DT to GND sets the dead time between the NDRV and AUXDRV signals.
2 DITHER/SYNC input Frequency dithering programming or synchronization input; a capacitor to GND and a resistor to RT set spread-spectrum dithering, or the pin takes the external sync pulse to synchronize the oscillator (synchronization up to 1.2MHz per the features list).
3 RT passive Switching frequency programming resistor connection; resistor RRT from RT to GND sets the PWM switching frequency (100kHz to 600kHz programmable per the features list).
4 FFB input Frequency foldback threshold programming input; a resistor to GND sets the output average current threshold below which the switching frequency folds back to 1/2 of its original value, and connecting it to GND disables foldback.
5 COMP passive Transconductance amplifier output and PWM comparator input, level shifted down to the PWM comparator inverting input, and actively pulled low by the controller after shutdown.
6 FB input Transconductance amplifier inverting input.
7 GND power_in Signal ground.
8 CSSC input Current sense with slope compensation input; a resistor from CSSC to CS programs the amount of slope compensation.
9 CS input Current-sense input for average current sense and cycle-by-cycle current limit, with a 400mV peak current-limit trip voltage and a -100mV reverse current-limit trip voltage.
10 PGND power_in Power ground that serves as the return path for the gate-driver switching currents.
11 NDRV output Main switch gate-driver output.
12 AUXDRV output pMOS active clamp switch gate-driver output, which can also drive a pulse transformer for synchronous flyback applications.
13 IN power_in Converter supply input with wide UVLO hysteresis; the features list an internal 18V zener clamp on the supply input.
14 EN input Enable input; the gate drivers are disabled and the device is in low-power UVLO mode when EN is below VENF, and above VENR the device checks other enable conditions.
15 DCLMP input Feed-forward maximum duty-cycle clamp programming input; a resistive divider from the input supply to GND sets the maximum duty cycle inversely proportional to the input supply voltage, with an 80% maximum limit per the features list.
16 SS passive Soft-start programming capacitor connection; the capacitor sets the soft-start period and hiccup-mode restart time, and a resistor to GND can set DMAX below 75%.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package TQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Bootstrap UVLO Wakeup Level (MAX5974A/C) VINUVR 15.4 16 16.5 V VIN rising 2
Bootstrap UVLO Shutdown Level VINUVF 6.65 7 7.35 V VIN falling, -40°C to +85°C 2
IN Clamp Voltage VIN_CLAMP 17 18.5 20 V IIN = 2mA (sinking) 2
IN Supply Current in Undervoltage Lockout (MAX5974A/C) ISTART 100 150 µA VIN = +15V, bootstrap UVLO, -40°C to +85°C 2
IN Supply Current After Startup IC 1.8 3 mA VIN = +12V, -40°C to +85°C 2
Enable Threshold Rising VENR 1.17 1.215 1.26 V VEN rising, -40°C to +85°C 3
Enable Threshold Falling VENF 1.09 1.14 1.19 V VEN falling, -40°C to +85°C 3
NDRV Switching Frequency Range fSW 100 600 kHz 3
NDRV Switching Frequency Accuracy -8 8 % 3
Maximum Duty Cycle DMAX 79 80 82 % fSW = 250kHz, -40°C to +85°C 3
Dithering Ramp Charging Current 45 50 55 µA VDITHER = 0V, -40°C to +85°C 3
Dithering Ramp Discharging Current 43 50 57 µA VDITHER = 2.2V, -40°C to +85°C 3
Soft-Start Charging Current ISS-CH 9.5 10 10.5 µA -40°C to +85°C 4
Soft-Start Discharging Current (normal shutdown) ISS-D 0.65 1.34 2 mA VSS = 2V, normal shutdown 4
Soft-Start Discharging Current (hiccup mode) ISS-DH 1.6 2 2.4 µA VSS = 2V, hiccup mode discharge for tRSTRT 4
Duty-Cycle Control Range (soft-start) VSS-DMAX 0 2 V DMAX (typ) = VSS-DMAX/2.43V 4
DCLMP Input Current IDCLMP -100 0 100 nA VDCLMP = 0 to 5V 4
Duty-Cycle Clamp Range VDCLMP-R 73 75.4 77.5 % VDCLMP = 0.5V 4
Duty-Cycle Clamp Range VDCLMP-R 54 56 58 % VDCLMP = 1V 4
Duty-Cycle Clamp Range VDCLMP-R 14.7 16.5 18.3 % VDCLMP = 2V 4
NDRV Pulldown Impedance RNDRV-N 1.9 3.4 Ω INDRV (sinking) = 100mA, -40°C to +85°C 4
NDRV Pullup Impedance RNDRV-P 4.7 8.3 Ω INDRV (sourcing) = 50mA 4
AUXDRV Pulldown Impedance RAUX-N 4.3 7.7 Ω IAUXDRV (sinking) = 50mA, -40°C to +85°C 4
AUXDRV Pullup Impedance RAUX-P 10.6 18.9 Ω IAUXDRV (sourcing) = 25mA 4
NDRV to AUXDRV Dead Time tDT 300 350 410 ns From NDRV falling to AUXDRV falling, RDT = 100kΩ 5
AUXDRV to NDRV Dead Time tDT 310 360 420 ns From AUXDRV rising to NDRV rising, RDT = 100kΩ 5
Cycle-by-Cycle Peak Current-Limit Threshold VCS-PEAK 375 393 410 mV 5
Cycle-by-Cycle Reverse Current-Limit Threshold VCS-REV -118 -100 -88 mV Turns AUXDRV off for remaining cycle if reverse current limit exceeded 5
Minimum On-Time tON-MIN 100 150 200 ns 5
Slope Compensation Current Ramp Height 47 52 58 µA -40°C to +85°C 5
PWM Comparator Offset Voltage VPWM-OS 1.35 1.7 2 V VCOMP - VCSSC, -40°C to +85°C 5
Current-Sense Gain ACS-PWM 3.1 3.33 3.6 V/V ΔVCOMP/ΔVCSSC (Note 4) 5
FB Reference Voltage (MAX5974A/B) VREF 1.5 1.52 1.54 V VFB when ICOMP = 0, VCOMP = 2.5V 6
FB Input Bias Current (MAX5974A/B) IFB -250 250 nA VFB = 0 to 1.75V 6
Transconductance (MAX5974A/B) gM 1.8 2.55 3.2 mS 6
Error Amplifier Source Current 300 375 455 µA VFB = 1V, VCOMP = 2.5V 6
Error Amplifier Sink Current 300 375 455 µA VFB = 1.75V, VCOMP = 1V 6
FFB Bias Current IFFB 26 30 33 µA VFFB = 0V, VCS = 0V (not in FFB mode), -40°C to +85°C 6
IN to GND -0.3 26 V VEN = 0V 2
RT, DT, FFB, COMP, SS, DCLMP, DITHER/SYNC to GND -0.3 6 V 2
FB to GND (MAX5974A/B only) -6 6 V 2
CS, CSSC to GND -0.8 6 V 2
PGND to GND -0.3 0.3 V 2
EN Maximum Input Current (continuous) 1 mA 2
Operating Temperature Range -40 85 °C 2
Maximum Junction Temperature 150 °C 2
Storage Temperature Range -65 150 °C 2
Lead Temperature (soldering, 10s) 300 °C Soldering, 10s 2
Soldering Temperature (reflow) 260 °C Reflow 2
Junction-to-Case Thermal Resistance θJC 7 °C/W 2

CAD (KiCad official)

  • Symbol: MAX5974AETE+T
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: TQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: max5974aete-t-etched.step / max5974aete-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max5974aete-t.step / max5974aete-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (28 pp, sha256 1c33faeee7c26a77, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF