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MAX5183BEEI+T

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Analog Devices Inc Maxim Integrated Digital To Analog Converters (DAC), QSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MAX5183BEEI+T

Analog Devices Inc Maxim Integrated · Digital To Analog Converters (DAC) · QSOP-28

MAX5183BEEI+T from Analog Devices Inc Maxim Integrated, in a QSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CREF1 passive Reference bias bypass for DAC1; the datasheet recommends bypassing it with a low-ESR 0.1µF capacitor to AVDD.
2 OUT1P output Positive analog output of DAC1, a current output on the MAX5180 and a voltage output on the MAX5183 (400mV full-scale differential).
3 OUT1N output Negative analog output of DAC1, a current output on the MAX5180 and a voltage output on the MAX5183 (400mV full-scale differential).
4 AGND power_in Analog ground; the substrate is connected to AGND and the device has separate analog and digital grounds joined at one point.
5 AVDD power_in Analog positive supply, 2.7V to 3.3V, to be decoupled with parallel 10µF and 0.1µF ceramic capacitors.
6 DACEN input DAC enable: with PD low, DACEN=0 enters standby and DACEN=1 powers up the DAC; with PD high the device is in shutdown.
7 PD input Power-down select: high (DVDD) enters shutdown mode, while low (DGND) selects standby or wake-up according to DACEN.
8 CS input Active-low chip select for the digital interface.
9 CLK input Clock input; DAC2 data is preloaded on the falling edge and DAC1 and DAC2 registers update on the rising edge, with fCLK up to 40MHz.
10 N.C. unconnected No connect; do not connect to this pin.
11 REN input Active-low reference enable; connect to DGND to use the on-chip 1.2V reference, or to AVDD to disable it for an external reference.
12 D0 input Data bit D0 (LSB) of the 10-bit DAC input word.
13 D1 input Data bit D1 of the 10-bit DAC input word.
14 D2 input Data bit D2 of the 10-bit DAC input word.
15 D3 input Data bit D3 of the 10-bit DAC input word.
16 D4 input Data bit D4 of the 10-bit DAC input word.
17 D5 input Data bit D5 of the 10-bit DAC input word.
18 D6 input Data bit D6 of the 10-bit DAC input word.
19 D7 input Data bit D7 of the 10-bit DAC input word.
20 D8 input Data bit D8 of the 10-bit DAC input word.
21 D9 input Data bit D9 (MSB) of the 10-bit DAC input word.
22 DVDD power_in Digital positive supply, 2.7V to 3.3V, to be decoupled with its own 10µF and 0.1µF capacitors.
23 DGND power_in Digital ground; connect to DGND plane separate from the analog ground, joined at a single point.
24 REFR input Reference input; the reference current-set resistor RSET connects here (9.6kΩ internal on the MAX5183, external on the MAX5180).
25 REFO bidirectional Reference output (1.2V when REN is grounded, 10µA drive capability) or external reference input; heavier loads require an external buffer.
26 OUT2N output Negative analog output of DAC2, a current output on the MAX5180 and a voltage output on the MAX5183 (400mV full-scale differential).
27 OUT2P output Positive analog output of DAC2, a current output on the MAX5180 and a voltage output on the MAX5183 (400mV full-scale differential).
28 CREF2 passive Reference bias bypass for DAC2; the datasheet recommends bypassing it with a low-ESR 0.1µF capacitor to AVDD.

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package QSOP-28
Category Data Acquisition
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Leakage Current -1 1 1 µA 2
Voltage Compliance of Output -0.3 0.8 V 2
Phase Mismatch Between DAC Outputs -0.15 0.15 degrees 2
Gain Mismatch Between DAC Outputs -1 1 %FSR 2
Integral Nonlinearity INL -2 0.5 2 LSB fCLK = 40MHz 2
Differential Nonlinearity DNL -1 0.5 1 LSB Guaranteed monotonic 2
Zero-Scale Error -2 2 LSB 2
Full-Scale Error -40 15 40 LSB 2
Full-Scale Output Current IFS 0.5 1 1.5 mA 2
Shutdown Current ISHDN 0.5 1 µA PD = 1, DACEN = X, digital inputs at 0 or DVDD 3
Standby Current ISTANDBY 1 1.5 mA PD = 0, DACEN = 0, digital inputs at 0 or DVDD 3
Digital Supply Current IDVDD 4.2 5 mA PD = 0, DACEN = 1, digital inputs at 0 or DVDD 3
Analog Supply Current IAVDD 2.7 5 mA PD = 0, DACEN = 1, digital inputs at 0 or DVDD 3
Digital Power-Supply Voltage DVDD 2.7 3.3 V 3
Analog Power-Supply Voltage AVDD 2.7 3.3 V 3
Output Voltage Range VREF 1.12 1.2 1.28 V 3
Digital Input Current IIN -1 1 µA 3
Digital Input Voltage Low VIL 0.8 V 3
Digital Input Voltage High VIH 2 V 3
DAC2 CLK Fall to DATA Hold Time tDH2 0 ns 3
DAC1 CLK Rise to DATA Hold Time tDH1 0 ns 3
DAC2 DATA to CLK Fall Setup Time tDS2 10 ns 3
DAC1 DATA to CLK Rise Setup Time tDS1 10 ns 3
Clock Low Time tCL 10 ns 3
Clock High Time tCH 10 ns 3
Clock Period tCP 25 ns 3
CS Fall to CLK Fall Time 5 ns 3
CS Fall to CLK Rise Time 5 ns 3
Full-Scale Output Voltage VFS 400 mV 2
Output Noise 10 pA/√Hz 2
Clock and Data Feedthrough 50 nVs 2
DAC-to-DAC Output Isolation -60 dB 2
Resolution N 10 Bits 2
Glitch Impulse 10 pV-s 2
Output Settling Time 25 ns 2
Current Gain IFS / IREF 8 mA/mA 3
Reference Supply Rejection 0.5 mV/V 3
Reference Output Drive Capability IREFOUT 10 µA 3
Output Voltage Temperature Drift TCVREF 50 ppm/°C 3
Digital Input Capacitance CIN 10 pF 3
PD Fall Time to VOUT 50 µs 3
DACEN Rise Time to VOUT 0.5 µs 3
Absolute max AVDD, DVDD to AGND, DGND AVDD, DVDD -0.3 6 V to AGND, DGND 2
Absolute max digital inputs to DGND -0.3 6 V to DGND 2
Absolute max OUT1P, OUT1N, OUT2P, OUT2N, CREF1, CREF2 -0.3 6 V to AGND 2
Absolute max VREF to AGND VREF -0.3 6 V to AGND 2
Absolute max AGND to DGND -0.3 0.3 V 2
Absolute max AVDD to DVDD -3.3 3.3 V 2
Absolute max maximum current into any pin 50 mA 2
Continuous Power Dissipation 725 mW 28-Pin QSOP, TA = +70°C 2
Power Dissipation Derating 9 mW/°C 28-Pin QSOP, above +70°C 2
Operating Temperature Range TA -40 85 °C MAX5183BEEI 2
Storage Temperature Range -65 150 °C 2
Lead Temperature 300 °C soldering, 10s 2
Internal output resistors (MAX5183 only) 400 Ω matched on-chip, MAX5183 only; tolerance not printed 8
Internal reference current-set resistor RSET (MAX5183 only) RSET 9.6 kΩ internal, MAX5183 only; tolerance not printed 8

CAD (KiCad official)

  • Symbol: MAX5183BEEI+T
  • Footprint: Package_SO:QSOP-28_3.9x9.9mm_P0.635mm
  • 3D model: QSOP-28, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.75 mm nominal SSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: max5183beei-t-etched.step / max5183beei-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max5183beei-t.step / max5183beei-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (14 pp, sha256 e80b41dad861ffcf, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF