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MAX491ECSD+T

Maxim Integrated · Pre-ordered Chips · SOIC-14

MAX491ECSD+T from Maxim Integrated, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	N.C.	unconnected	No connect; not internally connected.
2	RO	output	Receiver output: RO is high if A > B by 200mV and low if A < B by 200mV.
3	RE	input	Receiver output enable: RO is enabled when RE is low and high impedance when RE is high.
4	DE	input	Driver output enable: driver outputs Y and Z are enabled by bringing DE high and are high impedance when DE is low.
5	DI	input	Driver input: a low on DI forces Y low and Z high, and a high on DI forces Y high and Z low.
6	GND	power_in	Ground.
7	GND	power_in	Ground.
8	N.C.	unconnected	No connect; not internally connected.
9	Y	tri_state	Noninverting driver output, high impedance when DE is low.
10	Z	tri_state	Inverting driver output, high impedance when DE is low.
11	B	input	Inverting receiver input.
12	A	input	Noninverting receiver input.
13	N.C.	unconnected	No connect; not internally connected.
14	VCC	power_in	Positive supply: 4.75V ≤ VCC ≤ 5.25V.

Key specifications

Parameter	Value
Manufacturer	Maxim Integrated
Package	SOIC-14
Category	Interface ICs
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Driver Output Voltage (Y, Z; A, B)		-8		12.5	V		2
Receiver Input Voltage (A, B)		-8		12.5	V		2
Supply Voltage (VCC)	VCC			12	V		2
Control Input Voltage (RE, DE)		-0.5			V	upper limit VCC + 0.5V	2
Driver Input Voltage (DI)		-0.5			V	upper limit VCC + 0.5V	2
Receiver Output Voltage (RO)		-0.5			V	upper limit VCC + 0.5V	2
Storage Temperature Range		-65		160	°C		2
Lead Temperature				300	°C	soldering, 10 sec	2
Operating Temperature Range (MAX4__C__ commercial)		0		70	°C		2
Driver Common-Mode Output Voltage	VOC			3	V	R = 27Ω or 50Ω, Figure 8	2
Change in Magnitude of Driver Differential Output Voltage for Complementary Output States	ΔVOD			0.2	V	R = 27Ω or 50Ω, Figure 8	2
Change in Magnitude of Driver Common-Mode Output Voltage for Complementary Output States	ΔVOD			0.2	V	R = 27Ω or 50Ω, Figure 8	2
Input High Voltage	VIH	2			V	DE, DI, RE	2
Input Low Voltage	VIL			0.8	V	DE, DI, RE	2
Input Current	IIN1	-2		2	µA	DE, DI, RE	2
Differential Driver Output (no load)	VOD1	2		5	V		2
Differential Driver Output (with load)	VOD2	1.5		5	V	R = 50Ω (RS-422)	2
Receiver Differential Threshold Voltage	VTH	-0.2		0.2	V	-7V ≤ VCM ≤ 12V	2
Receiver Output High Voltage	VOH	3.5			V	IO = -4mA, VID = 200mV	2
Receiver Output Low Voltage	VOL			0.4	V	IO = 4mA, VID = -200mV	2
Three-State (high impedance) Output Current at Receiver	IOZR	-1		1	µA	0.4V ≤ VO ≤ 2.4V	2
Receiver Input Resistance	RIN	12			kΩ	-7V ≤ VCM ≤ 12V, all devices except MAX487E/MAX1487E	2
Driver Short-Circuit Current, VO = Low	IOSD2	35		250	mA	-7V ≤ VO ≤ 12V (Note 4)	3
Driver Short-Circuit Current, VO = High	IOSD1	35		250	mA	-7V ≤ VO ≤ 12V (Note 4)	3
No-Load Supply Current	ICC		300	500	µA	MAX490E/MAX491E, DE, DI, RE = 0V or VCC	3
ESD Protection (Human Body Model)		-15		15	kV	A, B, Y and Z pins, Human Body Model	3
Driver Rise or Fall Time	tR, tF	3	20	40	ns	Figures 10 and 12, RDIFF = 54Ω, CL1 = CL2 = 100pF	3
Driver Output Skew to Output	tSKEW		5	10	ns	Figures 10 and 12, RDIFF = 54Ω, CL1 = CL2 = 100pF	3
Driver Input to Output (tPLH)	tPLH	10	40	60	ns	Figures 10 and 12, RDIFF = 54Ω, CL1 = CL2 = 100pF	3
Driver Input to Output (tPHL)	tPHL	10	40	60	ns	Figures 10 and 12, RDIFF = 54Ω, CL1 = CL2 = 100pF	3
Driver Enable to Output High	tZH		45	70	ns		3
Driver Enable to Output Low	tZL		45	70	ns		3
Driver Disable Time from Low	tLZ		45	70	ns		3
Driver Disable Time from High	tHZ		45	70	ns		3
Receiver Input to Output (tPLH)	tPLH	20	60	150	ns		3
Receiver Input to Output (tPHL)	tPHL	20	60	150	ns		3
Receiver Enable to Output Low	tZL		20	50	ns		3
Receiver Enable to Output High	tZH		20	50	ns		3
Receiver Disable Time from Low	tLZ		20	50	ns		3
Receiver Disable Time from High	tHZ		20	50	ns		3
Maximum Data Rate	fMAX	2.5			Mbps		3

CAD (KiCad official)

Symbol: MAX491ECSD+T
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: max491ecsd-t-etched.step / max491ecsd-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max491ecsd-t.step / max491ecsd-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Maxim Integrated datasheet (16 pp, sha256 273f114f0ec895b5, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF