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MAX481ESA+T

Public Made by Adom

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Maxim Integrated Interface - Specialized, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MAX481ESA+T

Maxim Integrated · Interface - Specialized · SOIC-8

MAX481ESA+T from Maxim Integrated, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RO output Receiver output: RO goes high if A > B by 200mV and goes low if A < B by 200mV.
2 RE input Receiver output enable (active low): RO is enabled when RE is low and is high impedance when RE is high.
3 DE input Driver output enable: the driver outputs (A and B on this part) are enabled when DE is high and are high impedance when DE is low.
4 DI input Driver input: a low on DI forces output A low and B high, and a high on DI forces A high and B low.
5 GND power_in Ground reference for the device.
6 A bidirectional Noninverting receiver input and noninverting driver output; the receiver input impedance is 12kΩ standard (48kΩ for the 1/4-unit-load MAX487E/MAX1487E class), and the datasheet states a fail-safe logic-high RO when the input is open.
7 B bidirectional Inverting receiver input and inverting driver output; it is paired with A for the differential RS-485/RS-422 bus.
8 VCC power_in Positive supply: 4.75V ≤ VCC ≤ 5.25V.

Key specifications

Parameter Value
Manufacturer Maxim Integrated
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive supply voltage (pin description, 5V ±5%) VCC 4.75 5 5.25 V Positive supply, 4.75V ≤ VCC ≤ 5.25V 7
Operating temperature range, E grade (MAX4__E__) -40 85 °C MAX4__E__ / MAX1487EE__A 2
Supply voltage VCC 12 V 2
Control input voltage RE, DE -0.5 V Max printed as VCC + 0.5V 2
Driver input voltage DI -0.5 V Max printed as VCC + 0.5V 2
Driver output voltage Y, Z; A, B -8 12.5 V 2
Receiver input voltage A, B -8 12.5 V 2
Receiver output voltage RO -0.5 V Max printed as VCC + 0.5V 2
Storage temperature range -65 160 °C 2
Lead temperature (soldering) 300 °C Soldering, 10 sec 2
Driver common-mode output voltage VOC 3 V R = 27Ω or 50Ω, Figure 8 2
Change in magnitude of driver differential output voltage for complementary output states ΔVOD 0.2 V R = 27Ω or 50Ω, Figure 8 2
Change in magnitude of driver common-mode output voltage for complementary output states ΔVOD 0.2 V R = 27Ω or 50Ω, Figure 8 2
Input high voltage VIH 2 V DE, DI, RE 2
Input low voltage VIL 0.8 V DE, DI, RE 2
Input current IIN1 -2 2 µA DE, DI, RE 2
Differential driver output (no load) VOD1 5 V no load 2
Receiver differential threshold voltage VTH -0.2 0.2 V -7V ≤ VCM ≤ 12V 2
Receiver input resistance RIN 12 kΩ -7V ≤ VCM ≤ 12V 2
Receiver output high voltage VOH 3.5 V IO = -4mA, VID = 200mV 2
Receiver output low voltage VOL 0.4 V IO = 4mA, VID = -200mV 2
Three-state (high impedance) output current at receiver IOZR -1 1 µA 0.4V ≤ VO ≤ 2.4V 2
Driver short-circuit current, VO = Low IOSD2 35 250 mA -7V ≤ VO ≤ 12V (Note 4) 3
Driver short-circuit current, VO = High IOSD1 35 250 mA -7V ≤ VO ≤ 12V (Note 4) 3
Supply current in shutdown ISHDN 0.5 10 µA DE = 0V, RE = VCC 3
Driver input to output (tPLH) tPLH 10 40 60 ns Figures 10 and 12, RDIFF = 54Ω, CL1 = CL2 = 100pF 3
Driver input to output (tPHL) tPHL 10 40 60 ns Figures 10 and 12, RDIFF = 54Ω, CL1 = CL2 = 100pF 3
Driver output skew to output tSKEW 5 10 ns Figures 10 and 12, RDIFF = 54Ω, CL1 = CL2 = 100pF 3
Driver rise or fall time tR, tF 3 20 40 ns Figures 10 and 12, RDIFF = 54Ω, CL1 = CL2 = 100pF 3
Receiver input to output tPLH, tPHL 20 60 150 ns 3
Maximum data rate fMAX 2.5 Mbps 3
Time to shutdown tSHDN 50 200 600 ns Note 5 3
Driver enable to output high tZH 45 70 ns 3
Driver enable to output low tZL 45 70 ns 3
Driver disable time from low tLZ 45 70 ns 3
Driver disable time from high tHZ 45 70 ns 3
Receiver enable to output low tZL 20 50 ns 3
Receiver enable to output high tZH 20 50 ns 3
Receiver disable time from low tLZ 20 50 ns 3
Receiver disable time from high tHZ 20 50 ns 3

CAD (KiCad official)

  • Symbol: MAX481ESA+T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: max481esa-t-etched.step / max481esa-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max481esa-t.step / max481esa-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Maxim Integrated datasheet (16 pp, sha256 273f114f0ec895b5, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF