component

MAX4173TESA+

Public Made by Adom

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Maxim Integrated Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsmax4173tesa+factory-2.0.0extractor-text

Verified MAX4173TESA+

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MAX4173TESA+ · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 10-page datasheet
  • ✓distributor: lcsc C1348010, digikey MAX4173TESA+-ND, mouser 700-MAX4173TESA
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-61fimmb4/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ max4173tesa.kicad_sym✓ max4173tesa.kicad_mod✓ max4173tesa.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers max4173tesa: viewers · Ray 10d ago
max4173tesa-etched.glb Publish 0.1.0 · Ray 10d ago
max4173tesa-etched.step max4173tesa: factory component page (tier=mfr) · Ray 10d ago
max4173tesa-hero.glb max4173tesa: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
max4173tesa-hero.overlay.json Publish 0.1.0 · Ray 10d ago
max4173tesa.glb Publish 0.1.0 · Ray 10d ago
max4173tesa.kicad_mod Publish 0.1.0 · Ray 10d ago
max4173tesa.kicad_sym Publish 0.1.0 · Ray 10d ago
max4173tesa.lbr Publish 0.1.0 · Ray 10d ago
max4173tesa.step Publish 0.1.0 · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 10d ago

MAX4173TESA+

Maxim Integrated · Pre-ordered Chips · SOIC-8

MAX4173TESA+ from Maxim Integrated, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Supply voltage input operating from +3V to +28V, bypassed to GND with a 0.1µF capacitor.
2 N.C. unconnected No connection; not internally connected.
3 GND power_in Ground.
4 OUT output Voltage output proportional to VSENSE (VRS+ - VRS-) with an output impedance of approximately 12kΩ.
5 N.C. unconnected No connection; not internally connected.
6 RS- input Load-side connection for the external sense resistor, with a 0 to +28V common-mode range.
7 N.C. unconnected No connection; not internally connected.
8 RS+ input Power-side connection for the external sense resistor, with a 0 to +28V common-mode range.

Key specifications

Parameter Value
Manufacturer Maxim Integrated
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Voltage Range VCC 3 28 V Guaranteed by PSR test 2
Common-Mode Input Range VCMR 0 28 V 2
Common-Mode Rejection CMR 90 dB VRS+ > +2.0V 2
Supply Current ICC 0.42 1 mA VRS+ > +2.0V, VCC > 12V 2
Leakage Current IRS+, IRS- 0.3 3 µA VCC = 0V, VRS+ = 28V 2
Input Bias Current IRS+ 0 50 µA VRS+ > +2.0V 2
Input Bias Current IRS+ -350 50 µA VRS+ ≤ +2.0V 2
Input Bias Current IRS- 0 100 µA VRS+ > +2.0V 2
Input Bias Current IRS- -700 100 µA VRS+ ≤ +2.0V 2
Full-Scale Sense Voltage VSENSE 150 mV VSENSE = VRS+ - VRS- 2
Total OUT Voltage Error -24 -9 24 % VSENSE = +100mV, VCC = +12V, VRS+ = +0.1V 2
Total OUT Voltage Error -7.5 7.5 % VCC = +12V, VRS+ = +12V, VSENSE = +6.25mV (Note 4) 2
Total OUT Voltage Error 0.5 5.75 % VSENSE = +100mV, VCC = +12V, VRS+ = +12V 2
Total OUT Voltage Error 0.5 3.25 % VSENSE = +100mV, VCC = +12V, VRS+ = +12V, TA = +25°C 2
Out High Voltage VCC - VOH 0.8 1.2 V VCC = +3.0V, VRS+ = 28V, VSENSE = 250mV (Note 5) 2
OUT Low Voltage VOL 1.2 5 mV TA = +25°C 2
Bandwidth BW 1.7 MHz VSENSE = +100mV 3
Bandwidth BW 0.6 MHz VRS+ = +12V, VCC = +12V, CLOAD = 5pF, VSENSE = +6.25mV (Note 4) 3
Gain AV 20 V/V MAX4173T 3
Gain Accuracy ΔAV -2.5 0.5 2.5 % TA = +25°C 3
Gain Accuracy ΔAV 4 % VSENSE = +10mV to +150mV, VCC = VRS+ = 12V, TA = -40°C to +85°C 3
Input Offset Voltage VOS -3 0.3 3 mV TA = +25°C (Note 6) 3
OUT Settling Time to 1% of Final Value 400 ns VSENSE = +6.25mV to +100mV 3
OUT Settling Time to 1% of Final Value 800 ns VCC = +12V, VRS+ = 12V, CLOAD = 5pF, VSENSE = +100mV to +6.25mV 3
OUT Output Resistance ROUT 12 kΩ 3
Power-Supply Rejection PSR 60 84 dB VSENSE = 80mV, VRS+ ≥ +2V 3
Power-Up Time to 1% of Final Value 10 µs VSENSE = +100mV, CLOAD = 5pF 3
Saturation Recovery Time 10 µs VCC = +12V, VRS+ = 12V (Note 7) 3
VCC, RS+, RS- to GND VCC, RS+, RS- -0.3 30 V to GND 2
OUT to GND OUT -0.3 V Upper limit printed as (VCC + 0.3V) 2
Differential Input Voltage VRS+ - VRS- -0.3 0.3 V 2
Current into Any Pin -20 20 mA 2
Continuous Power Dissipation (8-Pin SO) 471 mW TA = +70°C 2
Operating Temperature Range -40 85 °C 2
Storage Temperature Range -65 150 °C 2
Lead Temperature 300 °C soldering, 10s 2
Soldering Temperature (reflow) 260 °C 2
Power Derating (8-Pin SO) 5.88 mW/°C derate above TA = +70°C 2

CAD (KiCad official)

  • Symbol: MAX4173TESA+
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: max4173tesa-etched.step / max4173tesa-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max4173tesa.step / max4173tesa.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Maxim Integrated datasheet (10 pp, sha256 57b0eb85aacada5e, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF