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MAX4091ASA+

Maxim Integrated · Operational Amplifier · SOIC-8

MAX4091ASA+ from Maxim Integrated, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 N.C. unconnected No connection; the pin is not internally connected.
2 IN- input Inverting input; the input common-mode range extends 50mV beyond the supply rails, and the outputs are guaranteed not to phase-reverse or latch up beyond the common-mode range.
3 IN+ input Noninverting input; the input common-mode range extends 50mV beyond the supply rails (VEE - 0.05V to VCC + 0.05V).
4 VEE power_in Negative supply; the device operates from a single 2.7V to 6V supply with VEE as ground, or from split supplies of ±1.35V to ±3V.
5 N.C. unconnected No connection; the pin is not internally connected.
6 OUT output Amplifier output; swings to within 15mV of the supplies with a 100kΩ load and drives 1kΩ loads, with stability maintained for capacitive loads above 2000pF.
7 VCC power_in Positive supply; operating range is 2.7V to 6V referenced to VEE, with a 0.1µF bypass capacitor recommended for single-supply operation.
8 N.C. unconnected No connection; the pin is not internally connected.

Key specifications

Parameter Value
Manufacturer Maxim Integrated
Package SOIC-8
Category Amplifiers
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Range VCC 2.7 6 V TA = +25°C; Inferred from PSRR test 2
Supply Current ICC 115 165 µA TA = +25°C; VCM = VCC/2; VCC = 2.7V 2
Supply Current ICC 130 185 µA TA = +25°C; VCM = VCC/2; VCC = 5V 2
Input Offset Voltage VOS 0.03 1.4 mV TA = +25°C; VCM = VEE to VCC 2
Input Bias Current IB 20 180 nA TA = +25°C; VCM = VEE to VCC 2
Input Offset Current IOS 0.2 7 nA TA = +25°C; VCM = VEE to VCC 2
Common-Mode Rejection Ratio CMRR 71 90 dB TA = +25°C; (VEE - 0.05V) ≤ VCM ≤ (VCC + 0.05V) 2
Power-Supply Rejection Ratio PSRR 86 100 dB TA = +25°C; 2.7V ≤ VCC ≤ 6V 2
Large-Signal Voltage Gain, sourcing AVOL 83 105 dB TA = +25°C; VCC = 2.7V, RL = 100kΩ, 0.25V ≤ VOUT ≤ 2.45V, sourcing 2
Large-Signal Voltage Gain, sinking AVOL 81 105 dB TA = +25°C; VCC = 2.7V, RL = 100kΩ, 0.25V ≤ VOUT ≤ 2.45V, sinking 2
Large-Signal Voltage Gain, sourcing AVOL 91 105 dB TA = +25°C; VCC = 2.7V, RL = 1kΩ, 0.5V ≤ VOUT ≤ 2.2V, sourcing 2
Large-Signal Voltage Gain, sinking AVOL 78 90 dB TA = +25°C; VCC = 2.7V, RL = 1kΩ, 0.5V ≤ VOUT ≤ 2.2V, sinking 2
Large-Signal Voltage Gain, sourcing AVOL 87 115 dB TA = +25°C; VCC = 5.0V, RL = 100kΩ, 0.25V ≤ VOUT ≤ 4.75V, sourcing 2
Large-Signal Voltage Gain, sinking AVOL 83 115 dB TA = +25°C; VCC = 5.0V, RL = 100kΩ, 0.25V ≤ VOUT ≤ 4.75V, sinking 2
Large-Signal Voltage Gain, sourcing AVOL 97 110 dB TA = +25°C; VCC = 5.0V, RL = 1kΩ, 0.5V ≤ VOUT ≤ 4.5V, sourcing 2
Large-Signal Voltage Gain, sinking AVOL 84 100 dB TA = +25°C; VCC = 5.0V, RL = 1kΩ, 0.5V ≤ VOUT ≤ 4.5V, sinking 2
Output Voltage Swing High VOH 15 69 mV TA = +25°C; RL = 100kΩ (Note 1) 2
Output Voltage Swing High VOH 130 210 mV TA = +25°C; RL = 1kΩ (Note 1) 2
Output Voltage Swing Low VOL 15 70 mV TA = +25°C; RL = 100kΩ (Note 1) 2
Output Voltage Swing Low VOL 80 220 mV TA = +25°C; RL = 1kΩ (Note 1) 2
Supply Voltage Range VCC 2.7 6 V TA = TMIN to TMAX; Inferred from PSRR test 3
Supply Current ICC 200 µA TA = TMIN to TMAX; VCM = VCC/2; VCC = 2.7V 3
Supply Current ICC 225 µA TA = TMIN to TMAX; VCM = VCC/2; VCC = 5V 3
Input Offset Voltage VOS -3.5 3.5 mV TA = TMIN to TMAX; VCM = VEE to VCC 3
Input Offset Voltage Tempco ΔVOS/ΔT -2 2 µV/°C TA = TMIN to TMAX 3
Input Bias Current IB -200 200 nA TA = TMIN to TMAX; VCM = VEE to VCC 3
Input Offset Current IOS -20 20 nA TA = TMIN to TMAX; VCM = VEE to VCC 3
Common-Mode Rejection Ratio CMRR 62 dB TA = TMIN to TMAX; (VEE - 0.05V) ≤ VCM ≤ (VCC + 0.05V) 3
Power-Supply Rejection Ratio PSRR 80 dB TA = TMIN to TMAX; 2.7V ≤ VCC ≤ 6V 3
Large-Signal Voltage Gain, sourcing AVOL 82 dB TA = TMIN to TMAX; VCC = 2.7V, RL = 100kΩ, 0.25V ≤ VOUT ≤ 2.45V, sourcing 3
Large-Signal Voltage Gain, sinking AVOL 80 dB TA = TMIN to TMAX; VCC = 2.7V, RL = 100kΩ, 0.25V ≤ VOUT ≤ 2.45V, sinking 3
Large-Signal Voltage Gain, sourcing AVOL 90 dB TA = TMIN to TMAX; VCC = 2.7V, RL = 1kΩ, 0.5V ≤ VOUT ≤ 2.2V, sourcing 3
Large-Signal Voltage Gain, sinking AVOL 76 dB TA = TMIN to TMAX; VCC = 2.7V, RL = 1kΩ, 0.5V ≤ VOUT ≤ 2.2V, sinking 3
Large-Signal Voltage Gain, sourcing AVOL 86 dB TA = TMIN to TMAX; VCC = 5V, RL = 100kΩ, 0.25V ≤ VOUT ≤ 4.75V, sourcing 3
Large-Signal Voltage Gain, sinking AVOL 82 dB TA = TMIN to TMAX; VCC = 5V, RL = 100kΩ, 0.25V ≤ VOUT ≤ 4.75V, sinking 3
Large-Signal Voltage Gain, sourcing AVOL 94 dB TA = TMIN to TMAX; VCC = 5V, RL = 1kΩ, 0.5V ≤ VOUT ≤ 4.5V, sourcing 3
Output Voltage Swing High VOH 75 mV TA = TMIN to TMAX; RL = 100kΩ (Note 1) 3
Output Voltage Swing High VOH 250 mV TA = TMIN to TMAX; RL = 1kΩ (Note 1) 3
Output Voltage Swing Low VOL 75 mV TA = TMIN to TMAX; RL = 100kΩ (Note 1) 3
Output Voltage Swing Low VOL 250 mV TA = TMIN to TMAX; RL = 1kΩ (Note 1) 3
Supply Voltage (VCC to VEE) 7 V 2
Input Current (IN+, IN-) -10 10 mA 2
Operating Temperature Range -40 125 °C 2
Storage Temperature Range -65 150 °C 2
Junction Temperature 150 °C 2
Lead Temperature 300 °C soldering, 10s 2

CAD (KiCad official)

  • Symbol: MAX4091ASA+
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: max4091asa-etched.step / max4091asa-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max4091asa.step / max4091asa.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Maxim Integrated datasheet (16 pp, sha256 af2f86e446af6fec, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF