component
MAX40660ATB
Public Made by Adomby adom
Maxim Integrated Special Purpose Amplifiers, TDFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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| max40660atb-etched.step | 3d ago |
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| verification.json | 3d ago |
MAX40660ATB
Maxim Integrated · Special Purpose Amplifiers · TDFN-10-EP(3x3)
MAX40660ATB from Maxim Integrated, in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCL | power_in | Power supply connection for the input current clamp; connect to VCC. |
| 2 | LP | input | Enable/low-power input: logic-high is normal operation and logic-low puts the device into low-power standby (VIH 2.0V min, VIL 0.8V max). |
| 3 | IN | input | Signal input; connect to the photodiode cathode through a coupling capacitor for positive cathode bias, or directly to the cathode for negative bias on the anode. |
| 4 | OFFSET | input | Offset adjustment current input that sinks current to adjust the effective input offset current; leave unconnected if offset adjustment is not needed. |
| 5 | GAIN | input | Gain select input: connect to GND for 25kΩ transimpedance and to VCC for 50kΩ transimpedance (logic levels VIL 0.8V max, VIH 2.0V min). |
| 6 | GND | power_in | Circuit ground. |
| 7 | OUTN | output | Negative 50Ω output; the voltage decreases as input current increases and the output should be AC-coupled or terminated to VCC. |
| 8 | OUTP | output | Positive 50Ω output; the voltage increases as input current increases and the output should be AC-coupled or terminated to VCC. |
| 9 | VCC | power_in | +3.3V supply voltage (VCC specified as +2.9V to +3.5V in the electrical characteristics). |
| 10 | GND | power_in | Circuit ground. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Maxim Integrated |
| Package | TDFN-10-EP(3x3) |
| Category | Amplifiers |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute maximum) | -0.3 | 3.6 | V | 4 | |||
| Current Into IN | -2 | A | 10ns pulse width, 0.5% duty cycle | 4 | |||
| Current Into IN, OFFSET (continuous) | -0.4 | 0 | mA | continuous | 4 | ||
| Current into LP, Gain (continuous) | -10 | 10 | mA | continuous | 4 | ||
| Current into OUTP and OUTN (continuous) | -20 | 20 | mA | continuous | 4 | ||
| Voltage at OUTN, OUTP | 0.3 | V | printed as VCC + 0.3V; value is offset above VCC | 4 | |||
| Voltage at GAIN, LP | -0.3 | 0.3 | V | printed as -0.3V to VCC + 0.3V; max is offset above VCC | 4 | ||
| Operating Temperature Range | -40 | 125 | °C | 4 | |||
| Operating Junction Temperature Range (die) | -40 | 150 | °C | die | 4 | ||
| Storage Temperature Range | -55 | 150 | °C | 4 | |||
| Soldering Temperature (reflow) | 260 | °C | reflow | 4 | |||
| Supply Voltage (recommended, VCC) | VCC | 2.9 | 3.3 | 3.5 | V | VCL = VCC; typical at VCC = +3.3V | 4 |
| Power Supply Current | ICC | 41 | 70 | mA | LP > 2.0V (logic-high) (Note 4) | 4 | |
| Power Supply Current | ICC | 8 | 13 | mA | LP < 0.8V (logic-low) (Note 4) | 4 | |
| VCL Quiescent Supply Current | 0.1 | 20 | µA | LP > 2.0V (logic-high) (Note 4) | 4 | ||
| Input Bias Voltage | VBIAS | 0.85 | 1 | V | IN and OFFSET | 4 | |
| Transimpedance Linearity | -10 | 2 | 10 | % | GAIN = GND (Note 2) | 4 | |
| Transimpedance | Z21 | 18 | 25 | 32 | kΩ | GAIN logic-low, IIN < 2µAP-P | 5 |
| Transimpedance | Z21 | 36 | 50 | 64 | kΩ | GAIN logic-high, IIN < 1µAP-P | 5 |
| Transimpedance in low-power standby | 300 | mΩ | In low-power standby mode: LP < VIL, IIN = 1µARMS, fIN = 100MHz | 5 | |||
| OFFSET Input Transimpedance | 18 | 25 | 32 | kΩ | GAIN logic-low, IOFFSET < 2µAP-P | 5 | |
| OFFSET Input Transimpedance | 36 | 50 | 64 | kΩ | GAIN logic-high, IOFFSET < 1µAP-P | 5 | |
| Overload Recovery Time | 2 | ns | 0 to -100mA input current | 5 | |||
| Input Logic 0 | VIL | 0 | 0.8 | V | GAIN, LP (Note 4) | 5 | |
| Input Logic 1 | VIH | 2 | V | GAIN, LP (Note 4); printed max is VCC | 5 | ||
| Logic Input Current Low | IIL | 0.001 | 1 | µA | GAIN, LP (Note 4) | 5 | |
| Logic Input Current High | IIH | 0.001 | 1 | µA | GAIN, LP (Note 4) | 5 | |
| Standby De-Assert Delay | 200 | ns | Time from LP > VIL to output common-mode voltage 90% of nominal value. Measured at OUTP and OUTN. | 5 | |||
| Output Common-Mode Voltage | -1.15 | -0.73 | -0.4 | V | printed as VCC - 1.15 / VCC - 0.73 / VCC - 0.40; values are offsets below VCC | 5 | |
| Differential Output Offset ΔVOUT | ΔVOUT | -200 | mV | IIN = 0mA, GAIN = GND | 5 | ||
| Differential Output Offset ΔVOUT | ΔVOUT | -400 | mV | IIN = 0mA, GAIN = VCC | 5 | ||
| Output Impedance | ZOUT | 40 | 50 | 60 | Ω | Single-ended | 5 |
| Maximum Differential Output Voltage Swing | VOUT(MAX) | 475 | 825 | 1290 | mV | IIN = 0mA to -200µA pulse, GAIN logic-low | 5 |
| Maximum Differential Output Voltage Swing | VOUT(MAX) | 500 | 920 | 1490 | mV | IIN = 0mA to -200µA pulse, GAIN logic-high | 5 |
| Input Resistance | RIN | 65 | Ω | 5 | |||
| Bandwidth (MAX40660) | BW | 300 | 490 | 660 | MHz | MAX40660, CIN = 0.5pF | 5 |
| Bandwidth (MAX40660) | BW | 70 | 165 | 280 | MHz | MAX40660, CIN = 10pF | 5 |
| Input Noise Density (MAX40660) | 2.1 | pA/√Hz | MAX40660, f = 10MHz, CIN = 0.8pF | 5 | |||
| Input Noise Density (MAX40660) | 2.8 | pA/√Hz | MAX40660, f = 10MHz, CIN = 10pF | 5 | |||
| Junction to Ambient (θJA), single-layer board | θJA | 54 | °C/W | 10 TDFN, single-layer board, JESD51-7 | 4 | ||
| Junction to Case (θJC), single-layer board | θJC | 9 | °C/W | 10 TDFN, single-layer board | 4 | ||
| Junction to Ambient (θJA), four-layer board | θJA | 41 | °C/W | 10 TDFN, four-layer board, JESD51-7 | 4 | ||
| Junction to Case (θJC), four-layer board | θJC | 9 | °C/W | 10 TDFN, four-layer board | 4 |
CAD (KiCad official)
- Symbol:
MAX40660ATB - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
max40660atb-etched.step/max40660atb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);max40660atb.step/max40660atb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Maxim Integrated datasheet (19 pp, sha256
fbb147daa6526961, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).